Single event upset hardened circuitry without sensitivity to...

Details Single event upset hardened circuitry without sensitivity to... Single event upset hardened circuitry without sensitivity to...

2007-05-08

2007-05-08

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Reliability

Fail-safe

C326S013000, C326S023000

Reexamination Certificate

active

11002163

ABSTRACT:
An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be coupled to overshoot-insensitive and undershoot-insensitive nodes of the logic circuitry, respectively. The undershoot-blocking module is operable to (i) receive from a first node of the logic circuitry a first signal event having a undershoot condition impressed thereon, and (ii) block it from passing to the overshoot-insensitive node. The overshoot-blocking module is operable to (i) receive from the first node a second signal event having an overshoot condition impressed thereon, and (ii) block it from passing to the undershoot-insensitive node. As such, further propagation of the overshoot and undershoot conditions are prevented.

REFERENCES:
patent: 5313094 (1994-05-01), Beyer et al.
patent: 6018450 (2000-01-01), Ahmad et al.
patent: 2002/0158674 (2002-10-01), Ang et al.

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