Single ended sense amplifier

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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Details

C365S185210

Reexamination Certificate

active

06813206

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a sense amplifier, especially a single ended sense amplifier without a pre-charged signal.
BACKGROUND OF THE INVENTION
The sense amplifier is engaged in receiving signals of a memory apparatus of a semiconductor, and generates output signals in an output terminal.
FIG. 1
is a circuit scheme of a single ended sense amplifier in prior art. As shown in
FIG. 1
, a single ended sense amplifier
10
comprises a sense switch unit
11
, an inverse logic unit
12
and a loading unit
13
. The sense switch unit
11
is in between the memory apparatus in the semiconductor and the output terminal of the sense amplifier to couple them together; besides it is usually a N-channel metal-oxide semiconductor (NMOS) to be as a channel switch for controlling a channel from the memory apparatus to the output terminal. The inverse logic unit
12
is between the memory apparatus and the sense switch unit
11
to turn on or off the sense switch unit
11
. Generally, the inverse logic unit
12
can be an inverter or a NOR gate or an inverse amplifier. The loading unit
13
couples with the sense switch unit
11
to share electric current of the sense switch unit
11
, and it is normally a N-channel metal-oxide semiconductor (NMOS) or a P-channel metal-oxide semiconductor (PMOS). The single ended sense amplifier
10
is restricted by the driving capability of the loading unit
13
, therefore it causes reacting speed being put bounds.
For solving the reacting speed problem, to add a pre-charged unit on output terminal of the single ended sense amplifier is the most common usage.
FIG. 2
is a circuit scheme of the single ended sense amplifier with pre-charging function. As shown in
FIG. 2
, a single ended sense amplifier
20
can be pre-charged via a pre-charging control signal through a transistor
24
to enhance the driving capability of the loading unit
13
, it is that the reacting speed of the single ended sense amplifier
20
has been improved. As the type of the single ended sense amplifier
20
, the pre-charging control signal is needful; besides, the signal ended sense amplifier
20
cannot be applied to any condition, for instance, the pre-charging control signal cannot be supplied.
SUMMARY OF THE INVENTION
According to aforesaid, the present invention is to offer a single ended sense amplifier without a pre-charging signal to improve reacting speed.
To achieve above objective, the single ended sense amplifier of the present invention comprises: a first loading unit, which is for current loading; a first sense switch unit, which is in between a memory apparatus of semiconductor and the first loading unit to couple them together, and connects to the first loading unit to form an output terminal in order to be as a channel switch for a channel from semiconductor memory apparatus to the output terminal of the sense amplifier; a second loading unit, which offers greater current loading than the first loading unit; a second sense switch unit, which is in between the semiconductor memory apparatus and the second loading unit to couple them together so as to supply charging needs; an inverse logic unit, which is among the semiconductor memory apparatus, the first and the second sense switch units for turning on and off the first and the second sense switch units.
As it can be seen, the second sense switch unit is capable to provide charging current to improve the reaction speed of the sense amplifier without a pre-charging control signal. Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. For instance, two independent inverse logic units control two sense switch units other than one inverse logic unit of the embodiment of the present invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure


REFERENCES:
patent: 5056063 (1991-10-01), Santin et al.
patent: 5495191 (1996-02-01), Lev et al.
patent: 6219290 (2001-04-01), Chang et al.
patent: 6411550 (2002-06-01), Nasu
patent: 2002/0105831 (2002-08-01), Lee et al.

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