Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-07-08
2004-11-23
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189050, C365S203000, C365S196000
Reexamination Certificate
active
06822919
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to sense amplifier circuits used in memory circuits, and more particularly, this invention relates to a sense amplifier circuits having a global data-bus line and reduced power consumption and noise.
BACKGROUND OF THE INVENTION
Sense amplifiers are often used in static random access memories (SCRAM) and other types of memories during the Read operation of data from a memory cell. The memory cells are etched onto silicon wafers in bit lines formed of columns and word lines formed as rows. The intersection of a bit line and word line form an address of the memory cell. During a write operation, a row line contains a charge that the capacitor/transistor should take to place a value at the address corresponding to a “1” or “0”. When reading, a sense amplifier determines the level of charge of the particular address. For example, if the charge is greater than 50% of a normal charge, the sense amplifier reads a “1.” Otherwise, the sense amplifier reads the charge as a “0”. A controller and counter tracks a refresh sequence based on the rows that have been accessed in a particular order.
In one type of sense amplifier circuit, the differential voltage produced by a memory cell is amplified by a sense amplifier and fed through a single line output driver, for example, a global data-bus line (GDB) such as disclosed in commonly assigned U.S. Pat. No. 5,619,466, the disclosure which is hereby incorporated by reference in its entirety.
In that type of sense amplifier circuit, a sense amplifier is coupled to a memory cell via data lines and amplifies the data. The circuit includes a read bus complement (RBC) and read bus true (RBT) line. An equalizer circuit is coupled to the sense amplifier and operable to receive an equalization signal to equalize the sense amplifier. An enable circuit is coupled to the sense amplifier and operable to receive an enable signal to enable the sense amplifier to amplify data.
During a read operation, the read bus complement and read bus true lines are equalized by a sense amplifier equalization (SAEQB) signal that is generated by an internal equalization control circuit during an equalization phase of operation. During this equalization phase, a sense amplifier enable (SAEN) signal is generated by an enable circuit at a “low” value such that the cross-coupled transistors forming the sense amplifier are not activated. After the read bus complement and read bus true lines are properly equalized, the sense amplifier equalization (SAEQB) line turns “high” corresponding to Vcc. One of the read buses, i.e., the read bus complement or read bus true, will be pulled towards ground or “low” by the memory cell. After proper development of the differential in the read bus complement and read bus true line, the sense equalization enable signal goes “high,” turning “ON” the cross-coupled transistor structure forming the sense amplifier and further pulling down the particular read bus and increasing the voltage differential between the read bus complement and read bus true line, reducing access time. This can create an extra and unnecessary transition during the equalization phase, increasing the power consumption of the overall sense amplifier circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to control the data output of a sense amplifier circuit as described above during the equalization phase to reduce unnecessary transitions at the data output.
The present invention advantageously provides a sense amplifier circuit for a memory cell that includes a sense amplifier that is operable to be coupled to a memory cell via data lines and operable to amplify data. It includes read bus complement and read bus true lines and a data output for outputting a data output signal. An equalization circuit is coupled to the sense amplifier and operable to receive an equalization signal to equalize the sense amplifier. An enable circuit is coupled to the sense amplifier and operable to receive an enable signal to enable the sense amplifier to amplify data. A control circuit is operable for disconnecting the data output from one of the read bus complement or read bus true lines and minimize unwanted transitions on the data output signal.
In one aspect of the present invention, the control circuit comprises a latch circuit that stores data when an enable signal comprises a low signal. It could be formed by at least one passgate circuit that is turned on and off by an enable signal. In yet another aspect of the present invention, the latch circuit is formed as first and second passgate circuits and first and second feedback circuits. The first latch circuit is off when the second latch circuit is on. The control circuit is operable from the enable circuit, in yet another aspect of the present invention. The control circuit can be operable for disconnecting the data output from the read bus complement line whenever there is an equalization. The data output preferably comprises a single line data output such as a global data-bus (GDB) line. The sense amplifier is formed as a pair of cross-coupled transistors of the type known to those skilled in the art.
A method aspect of the invention controls a sense amplifier circuit and comprises the steps of equalizing a sense amplifier with an equalization signal and disconnecting the data output from one of the read bus complement or read bus true lines during the equalization phase of the sense amplifier. An enabling signal is provided for enabling the sense amplifier. The data output can be disconnected from the read bus complement line. In yet another aspect of the present invention, the data output is disconnected from a control circuit that is operative with a line drive circuit through which the data output signal is passed. The data output can comprise a global data-bus line.
REFERENCES:
patent: 4894803 (1990-01-01), Aizaki
patent: 5473567 (1995-12-01), McClure
patent: 5487048 (1996-01-01), McClure
patent: 5619456 (1997-04-01), McClure
patent: 5619466 (1997-04-01), McClure
patent: 5864696 (1999-01-01), McClure
patent: 5986967 (1999-11-01), Furumochi et al.
Hur J. H.
Jorgenson Lisa K.
Nguyen Van Thu
Regan Christopher F.
STMicroelectronics Inc.
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