Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth from gaseous state combined with preceding...
Reexamination Certificate
2001-08-17
2002-09-03
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth from gaseous state combined with preceding...
C438S507000, C438S962000, C438S022000
Reexamination Certificate
active
06444546
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a single electron device; and, more particular, to a single electron transistor including weak links with bottleneck figure and etching damage, in the place of the conventional tunnel junctions of a single electron transistor, made from an ultra-thin metal film based on simple processes combined of lithography and etching processes. The single electron transistor is promising to embody integrated single electron circuits. The present invention also relates to a method for fabricating the same.
DESCRIPTION OF THE PRIOR ART
A single electron device is an ultimate scheme of electronic device in the purpose of controlling current with one electron. Concept about a single electron transistor similar to the conventional field effect transistor (FET) had already been proposed and there have been proceeded the researches about the devices in order to embody ultra large scale integrated memories or ultra low power digital circuits. There have also been proceeded the researches about the other various new functional devices or circuits using the same principle.
An example of the single electron device is a single electron transistor similar to the conventional FET, which will be described referring to
FIG. 1
schematically depicting it.
A very small electron island
120
is coupled with two nodes
110
and
130
through two tunnel junctions
115
and
125
, respectively, and coupled with an input node
140
through a capacitor
135
. The tunnel junctions between the electron island and the respective two nodes
110
and
130
are characterized by the resistances and capacitances of (R
1
, C
1
) and (R
2
, C
2
), respectively. A constant voltage, V
0
, is biased at the node
110
, and a control voltage V
g
is input at the node
140
of the capacitor
135
to control the characteristics of the electron island.
Such a structure is very similar to the conventional MOSFET. The two nodes
110
and
130
correspond to the source and drain respectively, and the input node
140
also corresponds to the gate.
FIG. 2
is a graph showing the characteristics of the single electron transistor as described above. The drawing shows the relation of the control voltage V
g
and the current I through the electron island via the tunnel junctions when a voltage V
o
is biased.
When the constant voltage V
o
is input at the node
110
and the voltage V
g
is input at the input node, namely gate
140
, the current I is a dependent function of the voltage V
g
with peak patterns having a period of e/C
g
. Here, the peak corresponding to MAX is a conducting state released of the Coulomb blockade, and the part of MIN is an insulating state derived from the Coulomb blockade. The drawing shows that the current is a period function of the voltage V
g
with a period of e/C
g
and that the charge amount induced by the capacitor
135
can be detected with the sensitivity as little as an elementary charge e. This means that the source-drain current is modified by the induced charge amount of an elementary charge. Accordingly, this is called as a single electron transistor.
The characteristics of the tunnel junctions are given with the resistors and capacitances of (R
1
, C
1
) and (R
2
, C
2
). Assumed that the capacitance of the capacitor
135
is given as C
g
, the conditions in which the phenomena shown in
FIG. 2
, namely, single electron tunnel phenomena occurs, are as follows.
R
i
>>h/e
2
≈26
K&OHgr;
(
i=
1, 2) (1)
e
2
/C
t
>>k
B
T, C
t
=C
1
+C
2
+C
g
(2)
Here, h is 6.63×10
−34
J sec as Plank constant, e is 1.60×10
−19
C as charge amount of electron, k
B
is 1.38×10
−23
J/K as Boltsmann constant, and T is Kelvin temperature with a unit of K.
The mathematical formula (1) is a required condition of single electron tunneling to discern each event of tunneling each electron from another event. The formula (2) is a condition that the electron entered into the island blocks another electron with thermal fluctuations from entering into the island against Coulomb energy. These requirements mean that the impedance of the single electron device itself should be several hundred k&OHgr; as known in the formula (1), and that in order to operate the device at room temperature, the size of the island should be less than several decade nanometers and, as a result, the total capacitance C
t
of the island
120
should be an order of aF (10
−18
Farad), as known in the formula (2).
As described above, the essential features of the single electron device are the size of the island
120
and the good characteristic tunnel junctions
115
and
125
. Here, the good characteristic tunnel junctions mean that the tunnel junctions should have the resistance R
i
and capacitance C
i
according to the formulae (1) and (2). At the present time, the fabrication methods of the single electron devices to satisfy these conditions are classified as two groups in terms of the used material: metals and semiconductors.
In the case of the metal material, Al or Nb is mainly used with double angle evaporation technique. At first, patterns are formed with a size less than several decade nm by electron beam lithography and metal is deposited to form the electron island and other electrodes ambient to the island. After that, the metal film is natural-oxidized to form a good oxide film on the surface. Subsequently, another layer of metal film is again deposited with slightly different angle to form the tunnel junction. This method is advantageous to fabricate a unit component. However, it is impossible to apply the method to the integration of single electron elements for practicing the single electron device, because of the complication of processes including three-stage levels and the limitation of double angle evaporation technique.
In the case of semiconductor, gates are fabricated on channel, using electron beam lithography (oxidation and etching in case of silicon) and the tunnel junction is inducible by the gate voltage. However, this also requires such several levels of fabrication processes that it has many difficulties in the integration of single electron elements.
As described above, the prior single electron device integration requires very difficult conditions in its fabrication. That is, it requires patterning technique of 10-nm level for operation at room temperature and tunnel junctions having a capacitance of about several aF and a resistance of about several decade k&OHgr;. With the present technique, the fabrication of separate components can be proceeded to apply it to analog device such as sensor and detector, current standards and the like. However, the fabrication of the integrated digital circuit, which is more utilized and larger in demand, can not be proceeded with the prior material and processes.
In order to obtain the digital signal treatment of the single electron device and the utility as memory device, the integration of the single electron elements is essential. Thus, to achieve such requirements, it is very important to develop the fabrication processes of the single electron device to be easy and simple.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a single electron device able to solve the above-described problems of the prior arts. The device has weak links with bottleneck figure in place of the tunnel junction of the prior device. The weak links are easily formed on the same substrate by simple processes and thus the integration of the single electron device can be easily achieved.
In accordance with an aspect of the present invention, there is provided a single electron device comprising: an insulating substrate; an ultra-thin metal film on the substrate; and a protecting insulating film on the metal film to protect the metal film, wherein the metal film comprises: a source region; an electron island coupled with the source region; a drain region coupled with the electron island; two weak links with bottlen
Lee Seong-jae
Park Kyoung-wan
Shin Mincheol
Electronics and Telecommunications Research Institute
Jacobson & Holman PLLC
Lebentritt Michael S.
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