Single-cycle variable period buffer manager for disk controllers

Details Single-cycle variable period buffer manager for disk controllers Single-cycle variable period buffer manager for disk controllers

1997-10-16

2000-12-05

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711 4, 711101, 711113, 710 1, 710 25, 710 32, G06F 1200

Patent

active

061579858

ABSTRACT:
The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic. The buffer manager synchronizes all requests from various sources, and utilizes a single clock cycle of varying periods to accommodate all speeds of RAMs with just one base synthesizer frequency in order to reduce the cost and maximize simplicity of the buffer manager design.

REFERENCES:
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patent: 5261058 (1993-11-01), Squires et al.
patent: 5291584 (1994-03-01), Challa et al.
patent: 5465343 (1995-11-01), Henson et al.
patent: 5553208 (1996-09-01), Murata et al.
patent: 5603002 (1997-02-01), Hashimoto

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