Single cycle read/write/writeback pipeline, full-wordline...

Details Single cycle read/write/writeback pipeline, full-wordline... Single cycle read/write/writeback pipeline, full-wordline...

2006-08-29

2006-08-29

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S149000, C365S207000

Reexamination Certificate

active

07099216

ABSTRACT:
A DRAM is disclosed which includes a single ended bitline structure, a single ended global bitline structure, primary sense amplifiers with data storage and data write-back capability and with capability to decouple from the global bitlines, a full-wordline I/O structure where essentially all memory cell that belong to the same wordline are being operated on, and a pipelined architecture. The DRAM further includes a small voltage swing design. The primary sense amplifiers can include more than one amplification stages. Such a DRAM is suitable for applications in conjunction with processors as an embedded DRAM.

REFERENCES:
patent: 6014338 (2000-01-01), Wang et al.
patent: 6075735 (2000-06-01), Sugibayashi
patent: 6108258 (2000-08-01), Chen et al.
patent: 6246622 (2001-06-01), Sugibayashi
patent: 6351419 (2002-02-01), Dietrich et al.
patent: 6480424 (2002-11-01), Issa
patent: 6552944 (2003-04-01), Fifield
patent: 6768692 (2004-07-01), Luk et al.
patent: 2005/0030817 (2005-02-01), Luk et al.

Affiliated with

Also associated with

Rating

Single cycle read/write/writeback pipeline, full-wordline... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single cycle read/write/writeback pipeline, full-wordline..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single cycle read/write/writeback pipeline, full-wordline... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3712599