Single-cycle multi-accessible interleaved cache

Details Single-cycle multi-accessible interleaved cache Single-cycle multi-accessible interleaved cache

1996-04-26

1998-06-02

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711108, 711131, 711145, G06F 1200

Patent

active

057617147

ABSTRACT:
An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

REFERENCES:
patent: 4724518 (1988-02-01), Steps
patent: 5295252 (1994-03-01), Torii et al.
patent: 5559986 (1996-09-01), Alpert et al.
patent: 5640534 (1997-06-01), Liu et al.
patent: 5689680 (1997-11-01), Whittaker et al.

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