Single computer distributed memory computing environment and...

Details Single computer distributed memory computing environment and... Single computer distributed memory computing environment and...

2006-05-23

2006-05-23

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000

Reexamination Certificate

active

07051158

ABSTRACT:
A computing environment for a device having a processor, a device memory and an operating system. A first process running in the operating system has a memory and a memory cache. A second process running in the operating system has a second process memory accessible to the first process. A communication channel between the first process and second process makes the second process memory available for the first process memory to use. The device memory is sectioned into memory blocks, each having a starting address. A block ID identifies the memory block. Data is stored in various memory units of the memory block. An offset ID identifies the memory unit. A DMCE Virtual address contains the offset ID, the block Id and a device ID for identifying the memory unit. The DMCE virtual address of a memory unit used for the memory function is copied into the memory cache.

REFERENCES:
patent: 5157778 (1992-10-01), Bischoff et al.
patent: 5914727 (1999-06-01), Horan et al.
patent: 6385668 (2002-05-01), Gaddess et al.
patent: 6912641 (2005-06-01), Chen et al.

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