Single chip multiple range pressure transducer device

Details Single chip multiple range pressure transducer device Single chip multiple range pressure transducer device

2001-12-06

2003-11-04

Whitehead, Jr, Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

C438S053000, C310S314000

Reexamination Certificate

active

06642594

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to pressure transducers, and more particularly to piezoresistive pressure transducers adapted to be operable over a wide range of applied pressures.
BACKGROUND OF THE INVENTION
It is known to be desirable to measure a wide range of pressures using a single pressure transducer device. It is also known that piezoresistive pressure transducers adapted to measure relatively large pressures disadvantageously suffer from a relatively poor resolution or sensitivity when measuring relatively low pressures. That is, as the span of a sensor increases, the resolution or sensitivity of that sensor at the low end of the span decreases. An example of such a piezoresistive sensor is taught in commonly assigned U.S. Pat. No. 5,614,678, entitled “HIGH PRESSURE PIEZORESISTIVE SENSOR” and issued Mar. 25, 1997, the entire disclosure of which is hereby incorporated by reference. The reference also includes in the art cited, many other patents concerning pressure transducers to the assignee hereof.
Referring to
FIGS. 4A-4C
, the first steps in fabricating a piezoresistive pressure transducer according to the '678 patent are depicted therein. The details of these processing steps are described in commonly assigned U.S. Pat. No. 5,286,671 entitled “FUSION BONDING TECHNIQUE FOR USE IN FABRICATING SEMICONDUCTOR DEVICES”, the entire disclosure of which is also incorporated herein by reference. Referring first to
FIG. 4A
, a pattern wafer
40
, which may be made of a single crystal semiconducting material
44
such as N-type silicon, is selected. Such wafers are commercially available and are well known in the art. The wafer
40
has high conductivity P+ (or P++) silicon areas
42
which have been created by diffusion using oxide and/or nitride masking and photolithography for example. After the diffusion process, the surface of the wafer
40
is treated with a conductivity-selective etch which does not attack the P+ stir (or P++) areas, leaving them raised from the surface as shown in FIG.
4
A.
Referring now to
FIG. 4B
, there is shown a carrier wafer
50
, which will eventually form the diaphragm of the transducer. Semiconducting material
53
is lightly doped N- or P-type silicon. An oxide layer
52
is grown on a surface of the wafer
53
using any well known oxidation technique. A typical technique for providing an oxide layer on a silicon substrate is implemented by heating the wafer
50
to a temperature of between 1000°-1300° C. and passing oxygen over the surface of the substrate
53
. The passivating oxide layer
52
in this case is silicon dioxide.
Referring now to
FIG. 4C
, the next step in the procedure is depicted. As shown therein, the pattern wafer
40
of
FIG. 4A
which contains the piezoresistive sensing elements
42
has been bonded to the carrier wafer
50
of
FIG. 4B
to form a composite wafer
55
. The bonding process is performed in accordance with the preferred fusion bonding technique disclosed in the incorporated '671 patent. The technique described herein mimics that disclosed in the '671 patent and utilizes the earlier described P+ (or P++) doped semiconducting material
42
of the pattern wafer
40
and the oxide layer
52
of the carrier wafer
50
as bonding layers. Typical bonding conditions which join the two wafers together are temperatures of between 900°-1000° C. and times of between 5 and 10 minutes.
Referring now to
FIG. 4D
, it can be seen that the N-type silicon layer of the pattern wafer
40
has been removed entirely down to the P+ (or P++) piezoresistive sensing elements
42
in a selective conductivity etching process which uses the oxide layer
52
of the carrier wafer
50
as an etch stop. Such selective conductivity etching processes are well known in the art and operate by means of etchants which selectively attack the low conductivity N-type material without etching or in any manner attacking the high conductivity P+ (or P++) layers. After this etching process, the raised pattern of P+ (or P++) piezoresistive sensing elements
42
is left bonded to the dielectrically isolating layer
52
of the carrier wafer
50
.
Referring now to
FIG. 4E
, the next step in the procedure is depicted. The semiconducting material
53
of the carrier wafer
50
is preferably a single crystal (100) semiconductor material which may be etched on the side opposite the sensing elements
42
using an isotropic or anisotropic etching technique. Both isotropic and anisotropic etching techniques are commonly practiced, and familiar to those skilled in the art. The etching process forms an aperture
68
, which defines the active
64
and non-active
54
diaphragm areas. The thickness or vertical dimension of the active diaphragm area
64
may be of any desired dimension depending upon the length of time that the etching process is allowed to take place. The aperture
68
is preferably etched such that some of the sensing elements
42
are positioned above the non-active or fixed diaphragm area
54
, and others are positioned above the active or deflecting diaphragm area
64
. Those sensing elements positioned above the non-deflecting diaphragm region are designated outer sensing elements
47
, while those sensing elements positioned above the deflecting diaphragm region are designated inner sensing elements
48
. The sensing elements
47
,
48
are preferably electrically coupled together in a Wheatstone bridge configuration as is well understood.
Referring now to
FIG. 4F
, there is shown the completed high pressure piezoresistive pressure transducer device
60
. The carrier wafer
50
, with the etched out aperture region
68
is secured to a supporting member
66
. The supporting member
66
may be fabricated from single crystal silicon or may be glass, for example. Of course, other suitable supporting materials can be used. The bonding of the supporting member
66
to the carrier wafer
50
may be accomplished by means of an anodic bonding technique such as the one described in U.S. Pat. No. 4,040,172 entitled “METHOD OF MANUFACTURING INTEGRAL TRANSDUCER ASSEMBLIES APPLYING BUILT IN PRESSURE LIMITING” issued to Anthony D. Kurtz et al. and assigned to Kulite Semiconductor Products, Inc., the assignee herein. The entire disclosure of the '172 patent is also incorporated herein by reference. The bond is typically formed by applying a high electrical voltage through the composite structure under low pressure and temperature, thus bonding the carrier wafer
50
to the supporting member
66
and completing the device. The central region
70
of the diaphragm area
64
and member
66
cooperatively serve as an overpressure stop when exposed to an overpressure which overly-deflects the active area
64
towards the support member
66
.
As set forth though, such a fabricated transducer can suffer from the aforementioned drawbacks. Accordingly it is an object of the present invention to provide a single chip multiple range pressure transducer operable over a broad range of pressures and which provides a high degree of sensitivity when being subjected to relatively low pressures.
SUMMARY OF THE INVENTION
A single chip multiple range pressure transducer device including: a wafer including a plurality of simultaneously formed thinned regions separated by a fixed portion, each of the thinned regions having a same minimum thickness but of at least one different planar dimension; and, a plurality of piezoresistive circuits formed on the wafer, each of the circuits being associated with and at least partially formed above one of the thinned regions; wherein, the thinned regions deflect a different amount upon application of a common pressure thereto, whereby, when excited each of the circuits provides an output indicative the common pressure over a different operating range when the associated thinned region deflects.


REFERENCES:
patent: 4040172 (1977-08-01), Kurtz et al.
patent: 4065970 (1978-01-01), Wilner
patent: 5286671 (199

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