Single-chip microcomputer with read clock generating...

Details Single-chip microcomputer with read clock generating... Single-chip microcomputer with read clock generating...

2007-01-30

2007-01-30

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S154000, C711S104000, C711S103000, C711S102000, C711S005000, C713S500000

Reexamination Certificate

active

10390763

ABSTRACT:
Flash ROMs operate at a speed slower than that of a CPU. In order to raise the operating speed of a single-chip microcomputer, therefore, interleaving is adopted and a plurality of flash ROMs are operated alternately to obtain an apparent operating speed equivalent to that of a CPU. Read clock generating circuits are placed in close proximity to clock input pins of respective ones of the flash ROMs and supply the flash ROMs with read clocks obtained by dividing down the frequency of a system clock. Delay ascribable to wiring is eliminated from the read clocks as a result.

REFERENCES:
patent: 4387424 (1983-06-01), Frediani et al.
patent: 4412285 (1983-10-01), Neches et al.
patent: 5610808 (1997-03-01), Squires et al.
patent: 6115823 (2000-09-01), Velasco et al.
patent: 6625748 (2003-09-01), Tanaka et al.
patent: 2002/0007439 (2002-01-01), Gharachorloo et al.
patent: 2002/0007443 (2002-01-01), Gharachorloo et al.

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