Single-chip microcomputer using adjustable timing to fetch data

Details Single-chip microcomputer using adjustable timing to fetch data Single-chip microcomputer using adjustable timing to fetch data

1997-06-09

2000-09-26

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 1, 712 32, 712 43, G06F 1200

Patent

active

061254312

ABSTRACT:
It is an object of the present invention to provide a one-chip microcomputer which permits the access time for an external memory to be equal to that for an internal memory. The one-chip microcomputer 10 includes an internal ROM 11, control circuit 12, output terminals 13, input terminals 14, control circuit 15, selector 16, instruction register 17, delay circuit 18, and fetch control signal select gate 19. For selection of the external ROM 30, a control arrangement 20 and a delay circuit 18 are employed in one embodiment to adjust the time at which ROM data is fetched by the instruction register 17, based on the delay time for accessing the external ROM 30.

REFERENCES:
patent: 5426759 (1995-06-01), Padgaonkar
patent: 5511176 (1996-04-01), Tsuha
patent: 5613144 (1997-03-01), Hall et al.
patent: 5615383 (1997-03-01), Caudel et al.
patent: 5623686 (1997-04-01), Hall et al.
patent: 5860016 (1999-01-01), Nookala et al.
patent: 5930523 (1999-07-01), Kawasaki et al.

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