Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-09-17
1999-10-05
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711117, G06F 1300
Patent
active
059639750
ABSTRACT:
The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.
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Boyle Douglas B.
Jones Edwin R.
Koford James S.
Rostoker Michael D.
Scepanovic Ranko
Chow Christopher S.
LSI Logic Corporation
Swann Tod R.
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