Single chip gate array

Details Single chip gate array Single chip gate array

1991-12-10

1992-09-08

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

365 51, 365 63, 36518905, 36523003, G11C 506

Patent

active

051464284

ABSTRACT:
A gate array integrated circuit on a single chip has a standardized memory cell array, in a matrix, and a plurality of basic cells constituting a gate array unit. The integrated circuit is standardized as to its interconnections except for the basic cells constituting the gate array and other components, such as input/output buffers associated with an application specific wiring of the basic cells of the gate array. Connection between the gate array unit and the memory cell array is through a data register and switching circuit that can buffer data and arrange for the transfer of data at a selected data width up to the number of bits in a word line of the memory cell array, to provide for sufficient independence of the memory cell array and all of its necessary circuitry from the specific application wiring of the gate array unit, so that the memory cell array may be standardized.

REFERENCES:
patent: 4675849 (1987-07-01), Kinoshita
patent: 4724531 (1988-02-01), Angleton et al.
patent: 4731758 (1988-03-01), Lam et al.
patent: 4737933 (1988-03-01), Chiang et al.
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4825414 (1989-04-01), Kawata
patent: 4855958 (1989-08-01), Ikeda
patent: 4945513 (1990-07-01), Ueda
Sawada et al., IEEE 1988 Custom Integrated Circuits Conference, "A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM", 1988 pp. 20.3.1-20.3.4.

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