Single-chip dynamic random access memory (DRAM) system and metho

Details Single-chip dynamic random access memory (DRAM) system and metho Single-chip dynamic random access memory (DRAM) system and metho

1997-10-01

2000-02-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365226, G11C 702

Patent

active

060288027

ABSTRACT:
To operate a dynamic random access memory (DRAM) system faster and to make the DRAM system smaller, a DRAM system includes a DRAM cell array having a first bit line connected to a DRAM cell, wherein the DRAM cell stores a first voltage which is less than a second voltage, and a sense amplifier portion having a second bit line and for amplifying data of the second bit line to the first voltage. The sense amplifier portion connects electrically the first bit line and the second bit line, supplies a third voltage which is greater than the second voltage to the second bit line when the first bit line and the second bit line are connected electrically, and stops supplying the third voltage before a voltage of the second bit line reaches the first voltage.

REFERENCES:
patent: 4413330 (1983-11-01), Chao et al.
patent: 5140199 (1992-08-01), Seo
patent: 5802002 (1998-09-01), Ienaga
patent: 5814851 (1998-09-01), Suh
patent: 5815430 (1998-09-01), Verhaeghe et al.

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