Single-channel bus system for multi-master use with bit cell syn

Details Single-channel bus system for multi-master use with bit cell syn Single-channel bus system for multi-master use with bit cell syn

1988-03-15

1989-12-12

Griffin, Robert L.

Multiplex communications

Wide area network

Packet switching

H04J 302

Patent

active

048872628

ABSTRACT:
Messages consisting of an arbitration field followed by a data field circulate in a single-channel bus system. The stations comprise a storage element for an intended delay time between a locally formed signal transition and a resultant detectable signal transition. The stations also comprise a continuous sequencer for the successive bit cells. When a signal transition is detected, the sequencers are loaded with the position of the storage element, so that they are synchronized. In the case of a transmission operation, the delay is measured, so as to update the contents of the storage element.

REFERENCES:
patent: 4429384 (1984-01-01), Kaplinsky
patent: 4463351 (1984-07-01), Chiarottino
patent: 4470110 (1984-09-01), Chiarottino et al.
patent: 4562573 (1985-12-01), Murano et al.
patent: 4593283 (1986-06-01), Uchino
patent: 4596025 (1986-06-01), Satoh
patent: 4715031 (1987-12-01), Crawford et al.
U. Kiencke et al., "Automotive Serial Controller Area Network", SAE Technical Paper Series No. 860391, International Congress and Exposition, Detroit, Michigan, Feb. 24-28, 1986, pp. 1-6.

Affiliated with

Also associated with

Rating

Single-channel bus system for multi-master use with bit cell syn does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single-channel bus system for multi-master use with bit cell syn, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single-channel bus system for multi-master use with bit cell syn will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2126761