Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reissue Patent
2006-01-20
2010-11-30
Nguyen, Hau H (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S572000, C345S562000, C345S656000
Reissue Patent
active
RE041967
ABSTRACT:
A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
REFERENCES:
patent: 4404552 (1983-09-01), Hirahata
patent: 4845662 (1989-07-01), Tokumitsu
patent: 4882683 (1989-11-01), Rupp et al.
patent: 4985848 (1991-01-01), Pfeiffer et al.
patent: 5062057 (1991-10-01), Blacken et al.
patent: 5063526 (1991-11-01), Kawaga et al.
patent: 5091721 (1992-02-01), Hamori
patent: 5119494 (1992-06-01), Garman
patent: 5129060 (1992-07-01), Pfeiffer et al.
patent: 5249267 (1993-09-01), Osaki
patent: 5280579 (1994-01-01), Nye
patent: 5311213 (1994-05-01), Kosugi
patent: 5353403 (1994-10-01), Kohiyama et al.
patent: 5408251 (1995-04-01), Kwon
patent: 5422997 (1995-06-01), Nagashima
patent: 5473348 (1995-12-01), Fujimoto
patent: 5487146 (1996-01-01), Guttag et al.
patent: 5526025 (1996-06-01), Selwan et al.
patent: 5712664 (1998-01-01), Reddy
patent: 5712999 (1998-01-01), Guttag et al.
patent: 5794016 (1998-08-01), Kelleher
patent: 5818417 (1998-10-01), Mattison
patent: 5860016 (1999-01-01), Nookala et al.
patent: 5943066 (1999-08-01), Thomas et al.
patent: 5945974 (1999-08-01), Sharma et al.
patent: 5966116 (1999-10-01), Wakeland
patent: 6101620 (2000-08-01), Ranganathan
patent: 6125431 (2000-09-01), Kobayashi
patent: 6205531 (2001-03-01), Hussain
patent: 6308248 (2001-10-01), Welker et al.
patent: 6417857 (2002-07-01), Finger et al.
Brannon Sherwood
Cheung Edmund
Ishii Takatoshi
LandOfFree
Single-block virtual frame buffer translated to multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single-block virtual frame buffer translated to multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single-block virtual frame buffer translated to multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4162982