Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1994-10-14
1998-11-10
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711129, 365 49, G06F 1208
Patent
active
058359486
ABSTRACT:
In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.
REFERENCES:
patent: 4905141 (1990-02-01), Brenza
patent: 4945512 (1990-07-01), Dekarske et al.
patent: 5005011 (1991-04-01), Perlmann et al.
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5235697 (1993-08-01), Steely, Jr. et al.
patent: 5293603 (1994-03-01), Mac Williams et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5367659 (1994-11-01), Iyngar et al.
patent: 5392414 (1995-02-01), Yung
patent: 5396619 (1995-03-01), Walton
patent: 5418922 (1995-05-01), Liu
patent: 5434992 (1995-07-01), Mattson
Collins Michael J.
Olarig Sompong P.
Ramsey Jens K.
Chan Eddie P.
Compaq Computer Corporation
Nguyen Hiep T.
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