Single and multistage stage fifo designs for data transfer synch

Details Single and multistage stage fifo designs for data transfer synch Single and multistage stage fifo designs for data transfer synch

1994-11-28

1998-09-15

Chin, Wellington

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

395250, 395872, 395877, H01J 100

Patent

active

058095217

ABSTRACT:
An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of the first memory means for storing data, and a third memory for storing data connected to the output of the second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

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