Single and multiple channel memory detection and sizing

Details Single and multiple channel memory detection and sizing Single and multiple channel memory detection and sizing

1998-05-18

1999-12-14

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

711105, 711 5, G06F 1200

Patent

active

060031212

ABSTRACT:
A method for BIOS code for detecting and grouping memory devices connected to one or more memory channels, comprising reading characteristics of a memory device and if the characteristics have not been previously read, then programming device ID and group ID registers based upon a device counter and a group counter, respectively. The method further includes steps for properly incrementing the device and group counters so that additional memory devices on the channel may be read and grouped.

REFERENCES:
patent: 5390308 (1995-02-01), Ware et al.
patent: 5701438 (1997-12-01), Bains
patent: 5748554 (1998-05-01), Barth et al.
patent: 5799209 (1998-08-01), Chatter
patent: 5913046 (1999-06-01), Barth et al.
Crisp, R, "Direct RAMBUS Technology: The New Main Memory Standard", IEEE Pub 0272-1732/97, 1997.
Garrett B, "RDRAMs: A New Speed Paradigm", IEEE Pub 1063-6390/94, 1994.
Crisp, R, "High Bandwidth RDRAM Technology Reduces System Cost", IEEE Pub 1063-6390/96, 1996.

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