Single and multilevel rework

Details Single and multilevel rework Single and multilevel rework

2003-01-21

2004-01-06

Nguyen, Ha Tran (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S752000, C257S759000, C257S760000, C257S762000, C438S004000

Reexamination Certificate

active

06674168

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to integrated circuit processing, and more particularly to methods relating to integrated circuit rework processes on semiconductor wafers
2. Related Art
Currently, integrated circuit BEOL (back end of the semiconductor processing rework processes are used for both ASIC (Application Specific Integrated Circuit) design and normal production. These rework processes have been developed for both and copper multi-level-metal wiring and are generally employed to correct yield or problems or a photomask error. Such rework processes enable QTAT (quicker turn time) design verification and save integrated circuit fabrication costs. An example of a process is given in U.S. Pat. No. 6,332,988, the complete disclosure of which is incorporated by reference, wherein a process for reworking electroplated solder bump is disclosed.
The introduction of copper and low dielectric (k) technologies presents the for additional rework process definition because the physical and chemical properties low k dielectric materials differ significantly from silicon dioxide, and therefore are not to the same rework procedures. Such rework processes must integrate with POR (process of record back-end-of-line) processing sequences, maintain planarity throughout rework process, remove multiple thin films including Si
3
N
4
, low k organic dielectrics, copper, liner materials, and stop on the top of the dielectric and tungsten interconnect region residing the electronically active devices such as transistors (typically called the front end). This dielectric is typically Boron-doped SiO2 or “BPSG”(Boron Phosphorous Silicate Glass). The BPSG, an electrical conductor fabricated of tungsten damascene is typically utilized so this can be abbreviated “BPSG/W.” Some conventional processes teach methods for a defective SiLK® layer caused by improper coating such as for a photoresist process. However, these conventional processes do not address rework of the final metal in addition to the dielectric BEOL.
Additionally, as integrated circuit device dimensions shrink with each successive the pitch at the lower wiring levels becomes challenging with respect to overlay shorting, via resistance of copper to copper vias in low k materials, line to metal line capacitance, and metal level to metal level cooling issues.
Therefore, there is a need for an integrated circuit rework process which results in vertical space between any or all BEOL levels, and which would be instrumental infacilitating removal and reconstruction of defective BEOL levels and in securing desired process latitude with respect to overlay, via resistance, line capacitance, and cooling.
SUMMARY OF INVENTION
The present invention has been devised, and it is an object of the present invention to provide a method for both a single chip wiring or interconnect metal level as well as multilevel rework processing.
There is provided, according to one aspect of the invention, a method of reworking BEOL (back end of a processing line) interconnect levels of damascene metallurgy, wherein each of the levels comprise a line portion and a via portion embedded in multiple dielectric layers. The method comprises sequentially removing the interconnect levels by selectively removing the multiple dielectric layers beginning with an uppermost dielectric layer. Then, the line and via portions of the interconnect levels are exposed. Next, the exposed line and via portions of the interconnect levels are coplanarized. Finally, the removed interconnect levels are replaced with full interconnect levels of damascene metallurgy.
Furthermore, the multiple dielectric layers are formed by stacking a first dielectric layer over a second dielectric layer, wherein the first dielectric layer comprises a lower dielectric constant material than the second dielectric layer. Also, the multiple dielectric layers are from the uppermost dielectric layer to a scratch stop layer, wherein the scratch stop layer is positioned below a lowest one of the BEOL interconnect levels. Moreover, the line and via portions form wiring conductors, wherein the wiring conductors comprise copper. Additionally, the line and via portions are removed at a faster rate than the multiple dielectric layers.
The method further comprises depositing a polish stop layer over the exposed line and via portions, wherein the polish stop layer enables removal of the line and via portions to a thickness coplanar with a lowermost dielectric layer. Furthermore, the multiple dielectric layers are formed to include a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer have different removal properties. Also, the via portion of the first interconnect level connects to the via portion of the second interconnect level, wherein the via portion of the first interconnect level is formed smaller than the via portion of the second interconnect level. Additionally, the method further comprises depositing a cap hardmask layer over the exposed line and via portions, wherein the cap hardmask layer comprises one of nitrides, oxides, Si
3
N
4
, TaN, Ta or W.
Alternatively, the method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, wherein the first dielectric layer comprises a lower dielectric constant material than the second dielectric layer.
The invention provides an integrated circuit structure that includes a first section comprising logical and functional devices and interconnection layers above the first section. Each of the interconnection layers comprises a first insulator layer, a second insulator layer above the first insulator layer and electrical wiring within the first insulator layer and the second insulator layer. The first insulator layer has a lower dielectric constant than that of the second insulator layer and the second insulator layer is harder than the first insulator layer.
The second layer comprises a protection layer that protects the first layer during rework operations performed on overlying layers of interconnections. The first insulator layer comprises an organic insulator. The second insulator layer comprises one of nitrides, oxides, Si
3
N
4
, TaN, Ta,W. The electrical wiring comprises damascene copper. Each grouping of the first insulator layer, the second insulator layer, and the electrical wiring comprise a single interconnection layer within the structure.
The invention further provides a method of reworking such interconnection layers above logical and functional layers of an integrated circuit structure. The method removes the upper insulator of a first interconnection layer and then removing the electrical wiring and the lower insulator of the first interconnection layer in a selective removal process that does not affect an upper insulator of a second interconnect layer positioned immediately below the first interconnect layer. The upper insulator protects a lower insulator of the second interconnect layer during the process of removing the electrical wiring and the lower insulator in the first interconnect. The process completely removes the first interconnection layer and leaves the interconnection layer in tact, and a replacement interconnect layer is formed in place of the first interconnect layer.
The process of removing the upper insulator also removes a portion of the lower insulator and exposes portions of the electrical wiring. After removing the upper insulator, the invention optionally depositing an etch stop layer on partially removed portions of the lower insulato

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