Single address queue for handling multiple priority requests

Details Single address queue for handling multiple priority requests Single address queue for handling multiple priority requests

1999-09-01

2000-11-28

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 3, 710126, 710128, 710129, 710244, 711111, 711112, 711118, 711149, 711151, 711169, 711202, 711206, 345521, G06F 1300

Patent

active

061548006

ABSTRACT:
An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1) log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue. Further, each output address selection circuit includes an output address list pointing to occupied storage locations in the main queue, and, the output address lists are updated each time an access request is stored in, or read out from, the main queue. The present embodiment further comprises a control circuit for determining a request type of each incoming request, and for transmitting addresses from the input address list to the output address lists each time an access request is stored in the main queue.

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