Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-09-15
2009-11-10
Connolly, Mark (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S500000, C368S046000, C368S155000
Reexamination Certificate
active
07617410
ABSTRACT:
A system, method and computer program product for synchronizing adjustment of a time of day (TOD) clock for a computer system having multiple CPUs, each CPU having an associated physical clock providing a time base for executing operations that is stepping to a common oscillator, and an associated logical TOD clock. The method includes detecting propagation of a carry at a pre-determined bit position of the physical clock associated with a CPU in the computer system; and, updating, in response to the detecting of the pre-determined bit position carry, a TOD-clock offset value (d) to be added to a physical clock value (Tr) value to obtain a logical TOD clock value (Tb) for use by a CPU in the system. In this manner, each CPU computes a new logical TOD clock value in synchronization—the new logical TOD clock value taking effect simultaneously for the multiple CPUs.
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Check Mark A.
Smith, Sr. Ronald M.
Campbell John E.
Connolly Mark
International Business Machines - Corporation
Scully , Scott, Murphy & Presser, P.C.
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