Simultaneous read and refresh of different rows in a DRAM

Details Simultaneous read and refresh of different rows in a DRAM Simultaneous read and refresh of different rows in a DRAM

1996-03-01

1999-04-06

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523005, 36523004, 365222, G11C 700

Patent

active

RE0361801

ABSTRACT:
A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.

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