Static information storage and retrieval – Read/write circuit – Simultaneous operations
Patent
1991-06-26
1994-03-01
Ham, Seungsook
Static information storage and retrieval
Read/write circuit
Simultaneous operations
365222, 36523004, G11C 700
Patent
active
052914437
ABSTRACT:
A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.
REFERENCES:
patent: 3846765 (1974-11-01), De Vries
patent: 4106108 (1978-08-01), Cislaghi et al.
patent: 4581720 (1986-04-01), Takemae et al.
patent: 4847809 (1989-07-01), Suzuki
Ham Seungsook
Micro)n Technology, Inc.
Starkweather Michael W.
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