Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2000-02-10
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S230030, C365S230040
Reexamination Certificate
active
06215705
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to electrically erasable and programmable non-volatile memories. More particularly, this invention relates to a method and circuit that speeds up the programming and program verification operations of a memory device by simultaneously programming in one bank and verifying the programming in another bank of a memory device.
Electronic systems typically include processors and memory. The memory is used to store instructions and data. In some systems, such as cellular phones, non-volatile memory is needed to ensure that the stored data is not lost even when the system is turned off. One non-volatile memory family is Read Only Memory (ROM), Programmable ROM (PROM), and Erasable-Programmable ROM (EPROM), with varying degrees of flexibility of use. ROM memories have high density, low power consumption, and high performance, but they are not in-system updateable. On the other hand is the volatile memory family of Random Access Memory (RAM), Dynamic RAM (DRAM), and battery-backed Static RAM (SRAM). The RAM family, however, is in-system updateable and has high performance, but it is volatile. DRAM stores temporary data, and SRAM integrates a battery to retain stored data when system power is removed. SRAM is considerably more expensive than DRAM. Electrically-Erasable-Programmable ROM (EEPROM) is a special kind of ROM that is in-system modifiable on a byte-by-byte basis, like RAM, but it is also non-volatile, like ROM.
Flash memory is one type of inherently nonvolatile memory, with no refresh or battery requirements, which can be read, erased, or programmed in units of memory such a sectors or banks. It is a variation of EEPROM which, unlike flash memory, is erased and rewritten at the byte level, which is slower than flash memory updating. Flash memory is often used to hold control code such as BIOS in personal computer. When BIOS needs to be changed, the flash memory can be updated in block (rather than byte) sizes, making it easy to update. Flash memory is used in digital cellular phones, digital cameras, LAN switches, PC cards for notebook computers, digital set-up boxes, embedded controllers, and other devices. Flash memory is in-system updateable. Its simpler cell architecture (only one transistor) gives it significant density advantages over both EEPROM and SRAM, and compares favorably with densities achieved by ROM and DRAM on analogous manufacturing processes. Finally, flash memory is the only approach to satisfy the desired characteristics of nonvolatility, upgradeability, high density, and low cost.
One problem with prior flash memories is that they do not provide sufficient random access. For example, prior flash memory devices typically do not allow a processor to perform a program-verify operation while a program operation is underway in the memory device. Typically, the processor periodically polls a status register of the flash memory device to detect the end of the program operation before initiating a program-verify operation of the memory device. That is, a processor should wait until a program cycle is complete before initiating a program-verify cycle, because both program and program-verify operations cannot be performed simultaneously.
While prior art memory systems allow simultaneous read and write operations, they suffer from the problem that they can only do asynchronous (not clocked) memory read operation in combination with another embedded memory operation, such as embedded memory program or embedded memory erase operations. Embedded memory operations are command-sequence-mode operations which are carried out by writing a specific address and data sequence into a sequence register. Because asynchronous memory read operation is not a command-sequence-mode (embedded) operation, rather it is a direct-mode-operation like a default operation, prior art memory systems are not capable of simultaneously performing two command-sequence-mode (embedded) operations such as memory erase, memory write, and memory program-verify operations. Therefore, there is a need for an efficient flash memory device that allows simultaneous embedded program and program-verify operations in the same cycle.
BRIEF SUMMARY
By way of introduction only, the present invention provides simultaneous program and program-verify operations for a non-volatile memory device. In one preferred embodiment, a memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes a set of memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. When one bank receives a program command, the internal state machine takes control and starts the program operation, while the other bank can be accessed for program-verify operation.
One preferred embodiment of the present invention is to split the memory into upper bank and lower bank. The data to be programmed is also split into even-addressed data words and odd-addressed data words. The even-addressed data words and the odd-addressed data words are programmed alternatively into upper bank and lower bank, respectively. After programming a word of data into either upper bank or lower bank, the processor initiates the program-verify operation of the same word of data, while simultaneously programming the next word of data into the other bank. This process is repeated over time until the last word of data is programmed and program-verified. Therefore, there is always a word of data being-verified while another word of data is being programmed, during the same cycle.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5263003 (1993-11-01), Cowles et al.
patent: 5495442 (1996-02-01), Cernea et al.
patent: 5847998 (1998-12-01), Buskirk
patent: 5867430 (1999-02-01), Chen et al.
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Le Thong
Nelms David
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