Simultaneous pipelined read with multiple level cache for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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C711S103000, C711S115000, C711S117000, C711S122000, C711S127000, C711S129000, C711S140000, C711S167000, C711S168000, C365S189050, C365S230030

Reexamination Certificate

active

07877566

ABSTRACT:
A read command protocol and a method of accessing a nonvolatile memory device having an internal cache memory. A memory device configured to accept a first and second read command, outputting a first requested data while simultaneously reading a second requested data. In addition, the memory device may be configured to send or receive a confirmation indicator.

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