Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-09
2004-08-31
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S643000, C438S653000, C438S675000, C438S685000, C438S688000
Reexamination Certificate
active
06784105
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor chip fabrication.
BACKGROUND OF THE INVENTION
Increasing semiconductor chip density has placed more components on the wafer surface, which has, in turn, decreased the area available for surface wiring of the components. This has led to multilevel metallization schemes using a stack of multiple metal layers on the wafer. A typical stack starts with a barrier layer formed by silicidation of the silicon surface to produce a lowered electrical resistance between the surface and the metal layer.
Barrier layers also prevent alloying of aluminum and silicon if aluminum is the conducting material of the metal layer. Both titanium-tungsten (TiW) and titanium nitride (TiN), as well as other materials, are typically used to form a barrier layer.
Sometimes a first layer of platinum silicide is formed on the exposed silicon before the TiW is deposited. TiW is usually sputter-deposited onto the wafer into the open contacts before the conducting material deposition (i.e., aluminum) takes place. The TiW deposited on the field oxide is normally removed from the surface during the aluminum etch step.
Titanium nitride layers can be placed on the wafer by several deposition techniques, including evaporation, and sputtering. A layer of titanium is normally required under TiN films to provide a high conductivity intermediate with silicon substrates.
With copper (Cu) metallization, the barrier is also critical. Copper inside the silicon ruins device performance. Barrier metals frequently used include TiN, tantalum (Ta), and tantalum nitride (TaN).
A typical wafer has a layer of some dielectric material, called an intermetallic dielectric layer (“IDL”), that provides the electrical isolation between metal layers. This layer may receive a masking step that etches new-contact holes, called “vias” or “plugs”, down to the first-level metal. Conducting plugs may also be created by depositing conducting material into the hole. The first-level metal layer is then deposited and patterned. The IDL/plug/metal deposition/patterning sequence is repeated for subsequent layers.
A multilevel metal system is more costly than a single level metal system. It is also of lower yield and requires greater attention to planarization of the wafer surface and intermediate layers to create good current-carrying leads. It is partly in accordance with this greater attention that processes have been developed to remove contaminating oxide buildup on the wafer (“native oxide”).
Semiconductor wafer fabrication thus involves processes in which one or more layers are formed on a dielectric wafer, often after an interconnect structure has been patterned onto the dielectric (a “hard mask”). Typically, metal is deposited on the wafer and selectively etched away. Successive layers of metal and semiconductor or dielectric form electrical components on the semiconductor wafer.
Prior to metal deposition, the surface of the wafer may require cleaning of native oxide. Such cleaning is conventionally performed in a separate sputtering chamber from that used for metal deposition. Moving the wafer from one deposition chamber to another incurs an increased chance of contamination of the wafer from the ambient environment, as well as an increase of cost of fabrication, since at least two chambers are required.
Conventional directional argon bombardment (“Ar sputtering”) is a common process used during deposition of metal barrier and seed layers on an interconnect structure. Ar sputtering processes are used for both metal deposition and as a “clean”.
Sputter deposition is a process that (in general) can deposit any material on any substrate. It is widely used to coat costume jewelry and put optical coatings on glasses and lenses. Sputtering takes place in a vacuum, and is a physical, not a chemical process. It is sometimes also referred to as physical vapor deposition. The foregoing description of sputter deposition is a general description, and is not intended to exclude alternative theories of how the sputtering process operates or any particular sputtering apparatus.
Sputter deposition conventionally takes place inside a vacuum chamber (“deposition chamber”), in which a solid slab, called a “target”, of the material desired to be deposited. The target is electrically grounded. Argon gas is introduced into the deposition chamber and is ionized to a positive charge. The positively charged Ar atoms (actually “ions”) are attracted to the grounded target and accelerate towards it. During the acceleration they gain momentum, which is force, and strike the target. At the target, a phenomenon called momentum transfer occurs. Just as a cue ball transfers its energy to other balls on the pool table, causing them to scatter, the Ar ions strike the slab of deposition material, causing its particles to scatter. Thus, the Ar atoms ‘knock off’ atoms and molecules from the target into the vacuum of the deposition chamber. This is the sputtering activity. The sputtered atoms or molecules scatter in the deposition chamber with some coming to rest on the wafer.
Sputtering is a favored method of depositing material on a wafer in a stepwise fashion, where an even coating is desired. Material arrives at the wafer with a wide range of angles to coat the wafer surface. Such “step” coverage is further improved by rotating and heating the wafer.
Clean and dry argon (or neon) is required to maintain film (coating) composition characteristics, and low moisture is required to prevent unwanted oxidation of the deposited film. The deposition chamber is loaded with the wafers and the pressure is reduced by pumps (pumped down) to approximately 1×10
−9
torr. The Ar is introduced and ionized. Control of the Ar amount entering the chamber is critical due to its effect of raising the pressure in the chamber. With the Ar and sputtered material in the deposition chamber, the pressure is raised to approximately 1×10
−3
torr. Chamber pressure is a critical parameter in the deposition rate of the system. Thus, deposition chambers are precision equipment with associated high costs of purchase, operation and maintenance. Also, most conventional deposition chambers require careful and time-consuming setup and operations.
The intention of conventional Ar sputter clean is to remove the native oxide on the surface of the wafer to which metal will be deposited. The Ar sputter clean may, however be performed on patterned dielectric or metals layers. It was observed that the bombardment of an Ar sputter clean always results in some potential problems.
When conventional Ar sputter clean is performed on a patterned wafer, damage may occur to the wafer. In
FIG. 2
, a profile view schematic of a wafer, before
200
and after
200
′ conventional Ar sputter clean is presented. The wafer
200
,
200
′ includes several features. It includes a hard mask
201
, and IDL
202
, and a metal
203
. After conventional Ar sputter clean, the wafer
200
′ may have damage to the hard mask
201
′, or to the IDL
202
′. Changes may also occur to the etching profile
204
′, as well as to the sidewalls
206
′. Moreover, the underneath metal may be splashed onto and even penetrate the IDL
205
′.
Damage may also occur to the wafer when conventional Ar sputter clean is performed on a metal layer. In FIG.
3
(
a
) an exemplary profile schematic of a wafer, before (
300
) and after (
300
′) performing conventional Ar sputter clean, is presented. The wafer
300
,
300
′ includes a hard mask
301
, and IDL
302
, and a metal
303
. After conventional Ar sputter clean, the wafer
300
′ may have deposited metal removed at the field
307
′, trench bottom
302
′ and tapered sidewall
306
′. Damage to the hard mask
301
′ or to the IDL
302
may also occur, as well as changes to the etching profile
304
′. Again, the underneath metal may be splashed onto the IDL and onto the deposited metal
305
′.
SUMMARY OF THE INVENTIO
Chanda Kaushik
Clevenger Larry
Cowley Andy
Fang Sunfei
Greco Stephen
Infineon Technologies North America Corp.
Lerner David Littenberg Krumholz & Mentlik LLP
Nguyen Thanh
LandOfFree
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