Simultaneous multi-threading in a content addressable memory

Details Simultaneous multi-threading in a content addressable memory Simultaneous multi-threading in a content addressable memory

2006-01-31

2009-06-30

Sough, Hyung S (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C370S392000

Reexamination Certificate

active

07555593

ABSTRACT:
A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.

REFERENCES:
patent: 6792502 (2004-09-01), Pandya et al.
patent: 2006/0126628 (2006-06-01), Li et al.

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