Simultaneous, mirror write cache

Details Simultaneous, mirror write cache Simultaneous, mirror write cache

1996-06-28

1998-09-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711162, 711129, 711130, 711131, 711168, 711150, 39518204, G06F 1208

Patent

active

058025618

ABSTRACT:
A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.

REFERENCES:
patent: 5126889 (1992-06-01), Walden
patent: 5544347 (1996-08-01), Yanai et al.
patent: 5640506 (1997-06-01), Duffy
patent: 5640530 (1997-06-01), Beardsley et al.
patent: 5649154 (1997-07-01), Kumar et al.

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