Simultaneous function dynamic random access memory device...

Details Simultaneous function dynamic random access memory device... Simultaneous function dynamic random access memory device...

2002-04-18

2003-11-04

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189040

Reexamination Certificate

active

06643212

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) memory devices and other ICs incorporating embedded memory. More particularly, the present invention relates to a simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like.
It has long been a goal of memory design to increase the performance of DRAM in order to support higher speed processors. One method of increasing DRAM performance is to increase the “read” and “write” data rate across the memory bus. SDRAM access times and burst data rates are constantly improving by manufacturing process “shrinks” and improved interconnect technology. Additionally, improved command bus utilization has been achieved by reducing the number of instructions needed to perform certain memory operations. In general, the fewer command cycles which are required for the execution of memory commands results in more bus cycles which are then available for memory data transfers.
To date, several approaches have been used to minimize the number of command cycles needed to access SDRAM devices and embedded arrays. One example is the use of “burst accesses” which utilize a single “read” or “write” command execution in order to read or write to multiple sequential words. Another technique for reducing the number of command cycles required to access SDRAMs is the use of an “auto-precharge” mode of operation. Auto-precharge is a programmable mode wherein a “precharge” operation automatically occurs at the end of a predetermined number of burst “read” or “write” cycles without requiring the assertion of an external “precharge” command. Similarly, the execution of a “refresh” command in SDRAMs results in the device automatically precharging at the end of the “refresh” operation.
Nevertheless, there are a number of applications, such as in conjunction with graphics processors, where performance could be greatly enhanced if the associated memory supported multiple command executions on a single clock cycle. As an example, a memory architecture that allows for simultaneous “read” and “write” operations (used primarily for read-modify-write cycles) may use a “write” address first-in, first-out (“FIFO”) register to capture a “read” address to be used later as a “write” address. See Hardee, K. et al.; “A 1.43 GHz Per Data I/O 16 Mb DDR Low-Power Embedded DRAM Macro for a 3D Graphics Engine”; 2001 IEEE International Solid-State Circuits Conference Digest of Technical Papers; pp 386-387 and ISSCC Visuals Supplement pp 316-317. Further, the concept of capturing the “read” address and using it at a later time via a pipeline is described in U.S. Pat. No. 5,996,052 issued Nov. 30, 1999 to Taniguchi et al. for: “Method and Circuit for Enabling a Clock-Synchronized Read-Modify-Write Operation on a Memory Array”.
While simultaneous “read” and “write” operations have been reported in specialty memories (and certain embedded memories) using posted “write” addresses as mentioned above, simultaneous “read”, “write”, “active” and “precharge” operations in response to external memory commands have apparently not been previously reported.
SUMMARY OF THE INVENTION
In this regard, the technique of the present invention advantageously enables the execution of “read”, “write”, “active” and “precharge” commands to a memory array on a single clock cycle. The technique disclosed herein is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the present invention provides for the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.
In accordance with the disclosure of the present invention, simultaneous commands are supported through the use of separate bank addresses. As a consequence, parallel “active”, “read”, “write” and “precharge” commands can be executed on the same clock (“CLK”) cycle with only simultaneous “active” and “precharge” commands being unable to be executed to the same bank during any given clock cycle.
In a particular representative embodiment disclosed herein, each “active”, “read”, “write” and “precharge” command has its own dedicated address field, including bank addresses. In this manner, each command can be simultaneously and independently executed during the same clock cycle resulting in much improved memory control bus utilization through this high level of parallel operation.
Through the use of separate “read” and “write” addresses together with separate bank addresses for “precharge” operations as well, multiple commands may be captured on one edge (e.g. the rising edge) of the clock signal and performed internally to the memory array in parallel. For example, in a conventional four bank memory the address fields are: BA<
0
,
1
> (bank address); RA<
0
:X> (row address) and CA<
0
:X> (column address). By contrast, and in accordance with the technique of the present invention, the following new address fields may be utilized: BAA<
0
,
1
> (bank address for “active” or row select); BAR<
0
,
1
> (bank address for “read” commands); BAW<
0
,
1
> (bank address for “write” commands); BAP<
0
,
1
> (bank address for “precharge”); RA<
0
:X> (row address); CAR<
0
:X> (column address for “read” commands) and CAW<
0
:X> (column address for “write” commands).
In this regard, the conventional row address strobe (“/RAS”); column address strobe (“/CAS”); write enable (“/WE”) and chip select (“/CE”) signals may be then replaced with “read”, “write”, “active” and “precharge” commands with the input/outputs (“I/Os”; “DATA IN” and “DATA OUT”) not being common. Used together with the aforementioned address commands, fully parallel memory operation results. While this internally parallel operation adds some extra address bussing over prior art techniques and results in a small increase in DRAM periphery area, it nevertheless allows for a two, three or four (or more) times increase in memory bandwidth.
Particularly disclosed herein is an integrated circuit device including a memory array comprising a plurality of memory banks and wherein the memory array receives a clock signal and a number of memory array command signals and is configured for reading data therefrom and writing data thereto. The memory array comprises: a row address input for specifying a row address within the memory array; at least one column address input for specifying a column address within the memory array; a bank address read input for specifying one of the memory banks from which data may be read at the specified row and column address; and a bank address write input for substantially concurrently specifying another one of the memory banks to which data may be written at the specified row and column address.
Also disclosed herein is an integrated circuit device including a memory array comprising a plurality of memory banks. The integrated circuit device comprises: a clock input for sequencing operations of said memory array; a command input for receiving at least read, write, active and precharge commands for the memory array; a row address input for specifying a row address within the memory array; first and second column address inputs for specifying independent column addresses for respectively reading data from and writing data to the memory array; and a plurality of bank address inputs, with each of the bank address inputs corresponding to one of the read, write, active and precharge commands.
Further disclosed herein is a method for accessing data in an integrated circuit device including a memory array comprising a plurality of memory banks. The method comprises the steps of: activating a first of the pluralit

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