Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-01-02
2007-01-02
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S150000, C711S167000, C711S168000, C711S143000, C365S189040, C365S189050, C365S233100, C365S185010, C714S763000
Reexamination Certificate
active
10875652
ABSTRACT:
A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.
REFERENCES:
patent: 4797813 (1989-01-01), Igarashi
patent: 5214777 (1993-05-01), Curry, Jr.
patent: RE36732 (2000-06-01), Miyamoto
patent: 6216205 (2001-04-01), Chin et al.
patent: 2003/0076719 (2003-04-01), Byeon et al.
Printout: Samsung Electronics, “128M x 8 Bit/ 64M x 16 Bit NAND Flash Memory”, 39 pages.
Adusumilli Vijaya P.
Tehrani Abbas S.
Telecco Nicola
Atmel Corporation
Lane Jack A.
Schneck Thomas
Schneck & Schneck
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