Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-01-21
1998-10-27
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711150, 711167, G06F 928
Patent
active
058290494
ABSTRACT:
A method of improving the performance of a computer processor by recognizing that two consecutive register instructions can be executed simultaneously and executing the two instructions simultaneously while generating a single data address and while performing exception checking on a single data address. During an instruction fetch process, two consecutive instructions are tested to determine if both are either register load instructions or register save instructions. If both instructions are load or save register instructions, the corresponding data addresses are tested to see if both data addresses are in the same double word. If both data addresses are in the same double word, then the instructions are executed simultaneously. Only one data address generation is required and exception processing is performed on only one data address. In one example embodiment, a simplified test rapidly ensures that both data addresses are in the same double word, but also requires the base addresses to be at an even word boundary. In a second embodiment, where the processor includes an alignment test as a separate test, an even more simple test rapidly ensures that both data address are in the same double word without checking alignment.
REFERENCES:
patent: 4381541 (1983-04-01), Baumann et al.
patent: 4438493 (1984-03-01), Cushing et al.
patent: 5283874 (1994-02-01), Hammond
patent: 5335330 (1994-08-01), Inoue
patent: 5416749 (1995-05-01), Lai
Johnson, Mike. "Superscalar Microprocessor Design", Prentice Hall, NJ. p. 20, 1991.
Knebel Patrick
Storey Mark R.
Undy Stephen R.
Walker William L.
Chan Eddie P.
Hewlett--Packard Company
Nguyen Than V.
Winfield Augustus W.
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