Simultaneous control of multiple I/O banks in an I2C slave...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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C709S236000

Reexamination Certificate

active

07934034

ABSTRACT:
Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.

REFERENCES:
patent: 5031095 (1991-07-01), Hara et al.
patent: 6799233 (2004-09-01), Deshpande et al.
patent: 7080266 (2006-07-01), D'Angelo et al.
patent: 2005/0114577 (2005-05-01), Beckhoff et al.
“AN469 12C/SMBUS General Purpose I/O Expanders” Philips Application Note, Koninklijke Philips Electronics N.V., 44 pgs. Jan. 20, 2005.
Deshpande A.: “Design of a Behavioral (Register Transfer level, RTL) Model of the Inter-Integrated Circuit or 12C-Bus Master-Slave Interface,” Thesis, Univ. of New Mexico, 135 pgs.(May 1999).
International Search Report for international patent appln. PCT/IB2006/051362 (Aug. 22, 2006).

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