Simultaneous and selective memory macro testing

Details Simultaneous and selective memory macro testing Simultaneous and selective memory macro testing

2004-07-15

2008-05-27

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S201000, C365S230030

Reexamination Certificate

active

07379349

ABSTRACT:
A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and operates in an active mode according to a corresponding active mode control signal; and a control unit for generating and outputting, in accordance with an input operation mode control signal, the active macro selection signals and the active mode control signals that correspond to the respective memory macros, so that two or more of the memory macros are activated simultaneously.

REFERENCES:
patent: 5959911 (1999-09-01), Krause et al.
patent: 6601199 (2003-07-01), Fukuda et al.
patent: 7176560 (2007-02-01), Motomochi
patent: 02-015490 (1990-01-01), None
patent: 03-058375 (1991-03-01), None
patent: 07-307100 (1995-11-01), None
patent: 11-231023 (1999-08-01), None
patent: 2000-133000 (2000-05-01), None
patent: 2001-101900 (2001-04-01), None
Japanese Office Action issued in Japanese Patent Application No. 2003-274652, mailed Apr. 24, 2007.

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