Simultaneous access and cache loading in a hierarchically...

Details Simultaneous access and cache loading in a hierarchically... Simultaneous access and cache loading in a hierarchically...

2005-04-26

2005-04-26

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S122000

Reexamination Certificate

active

06886078

ABSTRACT:
A hierarchically organized, compilable semiconductor memory circuit having multiple levels with simultaneous access and cache loading. A first level memory portion and at least a next level memory portion are provided as part of the semiconductor memory circuit, wherein the memory portions are associated with separate Data In (DIN) and Data Out (DOUT) buffer blocks for effectuating data operations. DIN buffer blocks of the first level and intermediate levels, if any, are provided with multiplexing circuitry that is selectively actuatable for providing data accessed in the next level memory portion to Local Data In (LDIN) driver circuitry, whereby the accessed data is simultaneously loaded into the first and intermediate levels. Accordingly, extra clock cycles are saved from cache loading of the data used for subsequent memory operations.

REFERENCES:
patent: 6675265 (2004-01-01), Barroso et al.
Shimpi, Anand “Intel Pentium III 1GHz”, Mar. 8, 2000, http://www.anandtech.com/showdoc.html?i=1191, p. 1-2.*
Handy, “The Cache Memory Book”, 2ndedition 1998 Academic Press pp. 43-49 and 89-94.

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