Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-31
2007-07-31
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10904056
ABSTRACT:
A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.
REFERENCES:
patent: 5161115 (1992-11-01), Teshima et al.
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 6816827 (2004-11-01), Xia et al.
patent: 7017068 (2006-03-01), McBride et al.
patent: 2005/0120278 (2005-06-01), Smith et al.
Blanco Rafael
Granato Suzanne
Kampf Francis A.
Massey Douglas T.
Canale Anthony J.
Schmeiser Olsen & Watts
Siek Vuthe
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