Simulation result verification method and simulation result...

Details Simulation result verification method and simulation result... Simulation result verification method and simulation result...

2006-05-09

2006-05-09

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07043707

ABSTRACT:
A simulation result verification method of the present invention compares a simulation result representing the relationship between the time and the output state at a given node, with condition information specifying the conditions for the output state of the given node over time, and evaluates the same. Accordingly, it is possible to determine whether the simulation result and the condition information agree with each other and it is not necessary to visually verify the relationship between the simulation result and the threshold value, thereby shortening the verification time and reducing possible errors in visual verification to a low level.

REFERENCES:
patent: 6473881 (2002-10-01), Lehner et al.
patent: 6694495 (2004-02-01), Hussain et al.
patent: 2002/0133796 (2002-09-01), Oda
patent: 2003/0217341 (2003-11-01), Rajsuman et al.
patent: 2004/0139406 (2004-07-01), Kasapi
patent: 2004/0210861 (2004-10-01), Kucukcakar et al.

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