Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-01
2007-05-01
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11009094
ABSTRACT:
A semiconductor device simulation method includes the step of storing, in a storage unit, a surface potential and threshold voltage obtained by computation, the step of computing thermal drain noise on the basis of the data of the surface potential and thermal drain noise stored in the storage unit, and the step of determining whether or not to reduce thermal drain noise, and reflecting the computation result in simulation of the model when it is determined that thermal drain noise is to be reduced. A drain current Idsof a MOSFET is calculated and substituted into a relational expression for a drain current noise spectrum density obtained from a Nyquist theorem equation, thereby calculating a thermal drain noise coefficient γ of the MOSFET by substituting the current Idsinto a relational expression for a thermal drain noise spectrum density which is obtained from the Nyquist logical equation.
REFERENCES:
patent: 5687355 (1997-11-01), Joardar et al.
patent: 5761082 (1998-06-01), Miura-Mattausch
patent: 6714027 (2004-03-01), Lui et al.
Tsividis, Y.; Masetti, G. “Problems in Precision Modeling of the MOS Transistor for Analog Applications”; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions; Jan. 1984 pp. 72-79.
Derek K. Shaeffer, et al., “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid-State Circuits, vol. 32, No. 5 May 1997, pp. 745-759.
H. Nyquist., “Thermal Agitation of Electric Charge in Conductors”, Physical Review, vol. 32, Jul. 1928, pp. 110-113.
R. P. Jindal., “Hot-Electron Effects on Channel Thermal Noise in Fine-Line NMOS Field-Effect Transistor”, IEEE Transactions on Electron Devices, vol. ED-33, No. 9, Sep. 1986, pp. 1395-1397.
Gerhard Knoblinger., “A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design”, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 831-836.
Y. Tsivids., “Operation and Modeling of the MOSFET Transistor”, The Mos Transistor in Dynamic Operation-Large Signal Modeling, 1999, pp. 325-331.
A. J. Scholten, et al., “Compact modeling of drain and gate current noise for RF CMOS”, IEDM, 2002, pp. 129-132.
Hosokawa Satoshi
Miura Mitiko
Ueno Hiroaki
Do Thuan
Semiconductor Technology Academic Research Center
LandOfFree
Simulation model for design of semiconductor device, thermal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simulation model for design of semiconductor device, thermal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simulation model for design of semiconductor device, thermal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3822420