Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-11
2008-03-11
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000, C324S765010
Reexamination Certificate
active
10933335
ABSTRACT:
There is disclosed a simulation model for designing a semiconductor device, comprising adding at least a part of a difference between a density of a carrier described in a quasi-static manner with respect to a voltage applied between electrodes at a first time and a density of the carrier described in a transient state at a second time before the first time to the carrier density at the second time in accordance with a running delay of the carrier between both the times to thereby describe the carrier density at the first time in the transient state with respect to a semiconductor element having the first and second electrodes. A current flowing between the electrodes is described as a sum of a current flowing between the electrodes in the quasi-static manner, and a displacement current between the electrodes.
REFERENCES:
patent: 5467291 (1995-11-01), Fan et al.
patent: 5652716 (1997-07-01), Battersby
patent: 6472233 (2002-10-01), Ahmed et al.
patent: 6526556 (2003-02-01), Stoica et al.
patent: 6553340 (2003-04-01), Kumashiro
patent: 6711723 (2004-03-01), Tsai et al.
patent: 6720768 (2004-04-01), Crozier et al.
patent: 6877043 (2005-04-01), Mallory et al.
patent: 6884333 (2005-04-01), Landau
patent: 2003/0170898 (2003-09-01), Gundersen et al.
Wu et al., “Non-quasi-static models including all injection levels and DC, AC, and transient emitter crowding in bipolar transistors”, Jan. 1991, Electron Devices, IEEE Transactions on, vol. 38, Issue 1, pp. 167-177.
Choi et al., “A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm”, Jul. 1994, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 13, Issue 7, pp. 899-908.
Enz, “An MOS transistor model for RC IC design valid in all regions of operation”, Jan. 2002, Microwave Theory and Techniques, IEEE Transactions on, vol. 50, Issue 1, Part 2, pp. 342-359.
Chai et al., “Comparison of quasi-static and non-quasi-static capacitance models for the four-terminal MOSFET”, Sep. 1987, Electron Device Letters, IEEE, vol. 8, Issue 9, pp. 377-379.
“A MOSFET Model for Circuit Simulation Based on Carrier-Transit Delay”, Noriaki Nakayama, Prepared in Jun. 2003, Presented at the Public Hearing on Dissertations of the Graduate School of Advanced Sciences of Matter, Hiroshima University, Jul. 25, 2003.
Noriaki Nakayama, et al. “A Self-Consistent Non-Quasi-Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response”, Jpn. J. Appl. Phys. vol. 42 Part 1, No. 4B, Apr. 2003, pp. 2132-2136.
Miura Mitiko
Nakayama Noriaki
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Rossoshek Helen
Semiconductor Technology Academic Research Center
Whitmore Stacy A
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