Simulation method for semiconductor circuit device and...

Details Simulation method for semiconductor circuit device and... Simulation method for semiconductor circuit device and...

2007-07-03

2007-07-03

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10502621

ABSTRACT:
A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias fate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ΔPD(t)=CD+BD·log(t) is calculated by using constants CDand BDdepending on the negative bias voltage, a recovery amount ΔPR(t)=CR+BR·log(t) is calculated by using constants CRand BRdepending on the bias free voltage, and the deterioration amount (ΔPD), the recovery amount (ΔPR) and a basic deterioration amount (XD) are summed up.

REFERENCES:
patent: 6587994 (2003-07-01), Yamaji
patent: 6594625 (2003-07-01), Hayashi
patent: 6795802 (2004-09-01), Yonezawa et al.
patent: 2003/0200071 (2003-10-01), Zhang et al.
patent: 2000-323709 (2000-11-01), None
patent: 2001-308317 (2001-11-01), None

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