Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-28
2003-10-07
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C327S198000
Reexamination Certificate
active
06631505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a simulation circuit for a MOS (Metal Oxide Semiconductor) transistor used for simulation testing, for example, the simulation circuit for the MOS transistor (that is, a transistor model) which can be suitably used for the simulation testing using a simulator such as a SPICE (Simulation Program with Integrated Circuit Emphasis) or a like and to a method for the simulation testing of the MOS transistor, a storage medium storing a netlist (that is, data information required to implement the transistor model on a computer) of the simulation circuit for the MOS transistor and the netlist of the simulation circuit for the MOS transistor.
The present application claims priority of Japanese Patent Application No. 2000-363909 filed on Nov. 29, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
Information about characteristics of a semiconductor (for example, a MOS transistor) is conventionally stated in a data book, product catalog, or a like and is provided to customers. In recent years, however, there are increasing cases in which the information about the characteristics of semiconductors and/or a netlist showing configurations of an equivalent circuit inside the MOS transistor are distributed via communication lines such as the Internet. Therefore, the customers, after having obtained information about the characteristics of semiconductors in outline from the data book or from homepages of the Internet and having in advance selected the MOS transistor being a candidate to be employed, acquire the netlist showing a simulation circuit of the selected MOS transistor via the Internet or a like and then do detailed simulation testing of an application circuit (that is, a user circuit), using the SPICE or a like, based on the simulation circuit for the MOS transistor whose information has been already acquired. Then, the customers determine the MOS transistor to be employed based on a result of the simulation testing.
Such the kind of simulation circuit for MOS transistors is disclosed by, for example, Siliconics Inc., which has a gate terminal Gas shown in FIG.
9
. As shown in
FIG. 9
, the gate terminal G is connected to a node N
1
to which a gate electrode of an n-channel type MOSFET (hereinafter referred to as an “NMOS”)
1
is connected. A source terminal S is connected to a node N
2
to which a source electrode and a bulk electrode of the NMOS
1
are connected. Between the node N
1
and node N
2
is connected a gate/source capacitor
2
(the capacitor being connected between the gate and source). To the node N
2
is connected an anode of a drain/source diode
3
(the diode being connected between the drain and source) and to a node N
4
is connected a cathode of the drain/source diode
3
. A drain terminal D is connected to the node N
4
. The node N
4
is connected to a node N
3
through a drain resistor
4
. To the node N
3
is connected a drain electrode of the NMOS
1
. To the node N
4
is connected a bulk electrode of a p-channel type MOSFET (hereinafter referred to a “PMOS”)
5
. A gate electrode of the PMOS
5
is connected to the node N
1
. Both a drain electrode and source electrode of the PMOS
5
are connected to the node N
2
so that a parasitic diode of the PMOS
5
does not operate.
In the simulation circuit of the MOS transistor, a capacitor made up of the PMOS
5
serves as a feedback capacitor formed between the gate electrode and the drain electrode of the NMOS
1
. The simulation circuit is used for the simulation testing using the SPICE.
FIGS. 10 and 11
are diagrams showing results of the simulation testing done using the conventional simulation circuit for MOS transistors of
FIG. 9. A
feedback capacitance Crss is plotted as the ordinate and a voltage between the drain and gate VDG (hereinafter a “drain-gate voltage VDG”) as the abscissa. In
FIG. 10
, a result is shown which has been obtained by calculating a value of the feedback capacitance Crss based on a current flowing through the feedback capacitor when the drain-gate voltage VDG is changed from 40 V to −10 V at a rate of 1 V/&mgr;s. In
FIG. 11
, a result is shown which has been obtained by calculating a value of the feedback capacitance Crss based on a current flowing through the feedback capacitor when the drain-gate voltage VDG is changed from 40 V to −10 V at a rate of 1 V
s.
FIG. 12
is a circuit diagram showing electrical configurations of another conventional simulation circuit for MOS transistors disclosed by IR Inc. The disclosed simulation circuit for MOS transistors, as shown in
FIG. 12
, has a gate terminal G which is connected to a node N
2
. Between the node N
2
and a node N
7
is connected a resistor
11
and to the node N
7
is connected a gate electrode of an NMOS
12
. A source electrode and a bulk electrode of the NMOS
12
are connected to a node N
8
which is connected to a node N
3
through a resistor
13
. To the node N
3
is connected a source terminal S. To the node N
3
is connected an anode of a diode
14
. A cathode of the diode
14
is connected to a node N
1
. Between the node N
3
and node N
1
is connected a resistor
15
. To the node N
1
is connected a drain terminal D. The node N
1
is connected to a node N
9
through a resistor
16
and to the node N
9
is connected a drain electrode of the NMOS
12
.
To the node N
7
is connected a minus input terminal of a voltage-controlled type voltage source
17
. To the node N
9
is connected a plus output terminal of the voltage-controlled type voltage source
17
. The plus output terminal of the voltage-controlled type voltage source
17
is connected to a node N
10
and between the node N
10
and a node N
5
is connected a resistor
18
. To the node N
5
is connected a cathode of a diode
19
and an anode of the diode
19
is connected to a node N
0
. The node N
0
is connected to a port of a ground and to the minus output terminal of the voltage-controlled type voltage source
17
. Between the node N
10
and a node N
11
is connected a capacitor
20
. Between the node N
10
and a node N
6
is connected a resistor
21
. To the node N
5
is connected a cathode of a diode
22
and an anode of the diode
22
is connected to a node N
4
. To the node N
6
is connected a cathode of a diode
23
and an anode of the diode
23
is connected to the node N
0
.
To the node N
11
is connected an anode on an input side of a current-controlled type current source
24
and to the node N
6
is connected a cathode on an input side of the current-controlled type current source
24
. An anode on an output side of the current-controlled type current source
24
is connected to the node N
9
and a cathode on an output side of the current-controlled type current source
24
is connected to the node N
7
. To the node N
4
is connected an anode on an input side of a current-controlled type current source
25
and to the node N
0
is connected a cathode on an input side of the current-controlled type current source
24
. An anode on an output side of the current-controlled type current source
25
is connected to the node N
9
and a cathode on an output side of the current-controlled type current source
25
is connected to the node N
7
.
The voltage-controlled type voltage source
17
receives an input of a drain-gate voltage VDG being a voltage between a gate electrode and a drain electrode of the NMOS
12
and outputs an output voltage V
17
having the same value as the drain-gate voltage VDG. In the resistor
18
, when there is no current flow through the diode
19
(that is, when the drain-gate voltage VDG>−VF, where VF is a forward voltage of the diode
19
), almost no voltage drop occurs. Therefore, almost all the output voltages V
17
are applied to the diodes
19
and
22
. At this point, a current produced by junction capacitance of the diode
22
flows through the diode
22
. Moreover, when the drain-gate voltage VDG<−VF, where VF is the forward voltage VF of the diode
19
, a current
Do Thuan
Garbowski Leigh M.
NEC Electronics Corporation
Scully Scott Murphy & Presser
LandOfFree
Simulation circuit for MOS transistor, simulation testing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simulation circuit for MOS transistor, simulation testing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simulation circuit for MOS transistor, simulation testing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3154139