Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-26
2003-12-02
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06658640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrated circuits, and specifically to using simulation for feed forward process control during integrated circuit fabrication.
2. Discussion of the Related Art
A wafer fabrication company expends enormous resources to optimize its production processes for each technology node. A technology node refers to a set of processes that are based on a certain minimum feature size, i.e. critical dimension (CD), and requires the variance in that CD to be tightly controlled. For example, a wafer fabrication company may optimize its production process using 193 nm lithography technology with an acceptable line width variance of +/−20 nm. To optimize its production for each process, the wafer fabrication company uses a particular set of parameters for various pattern-defining processes during integrated circuit fabrication.
FIG. 1
illustrates a graph
100
plotting critical dimension (CD) values (x-axis) versus occurrences (y-axis) for a given process. The wafer fabrication company can develop a curve
101
based on a wide range of masks (or reticles in step-and-repeat projection systems, also referenced as masks herein; also as used herein the term stepper will refer to both stepper systems as well as step-and-repeat projection systems or scanners), wherein any mask having CD values between CD lower limit
102
and CD upper limit
103
would be considered an acceptable mask for that process. Of interest, each mask can demonstrate its own unique CD variation. For example, curves
104
and
105
represent CD variations for two different masks. Note that these CD variations are within CD lower limit
102
and CD upper limit
103
. Therefore, the masks having these variations would be acceptable for the process(es) developed by the wafer fabrication company for that specific technology node.
Unfortunately, a process applicable to multiple masks can result in undesirable variations on the printed wafer and limits the ability to extract the optimal performance for a given mask. For example, assume that the two masks having the CD values represented by curves
104
and
105
are used to produce the same layer of an integrated circuit. In such a case, it would be desirable that curves
104
and
105
be identical to ensure that the printed wafers produced from such masks are as identical as possible. Moreover, even assuming these masks are for different layers or for different integrated circuits, it would be desirable for the process to minimize the range of CD values on each mask, thereby improving the functionality of that mask. Finally, as the features continue to be manufactured smaller, the effect of such mask CD variations on the printed wafer undesirably increases.
To minimize the effect of CD variations on a mask, users can currently print multiple wafers to determine the best lithographic and/or other pattern-defining parameters for that mask. However, this repetitive process is extremely time-consuming as the number of variables to consider is large and their interaction is complicated. Moreover, using the fabrication equipment and associated tools merely for optimizing parameters undesirably reduces the time that the equipment can be used for their intended function, i.e. to fabricate integrated circuits.
Therefore, a need arises for a method of automatically customizing a process for each mask to account for its unique CD variations.
SUMMARY OF THE INVENTION
The current complexity associated with wafer processing in the sub-wavelength environment requires tight control over all parameters within the process to achieve yielding devices at a reasonable cost. In accordance with one aspect of the invention, a method of providing information to downstream wafer fabrication processes allows each process to be customized based on the mask being used. The method comprises capturing an image of a mask, simulating a wafer image of the mask, generating a mask map of information based on the simulation, and providing the mask map to a downstream wafer fabrication process when such process involves the mask. Generating the mask map can include determining a critical dimension variance and/or an edge error variance for the mask. The downstream wafer fabrication process can include at least one of a lithographic process, a resist process, and an etch process.
Providing the mask map to the downstream wafer fabrication processes can include indicating a location of each element in the mask map. For example, in one embodiment, an identification code could be used on the mask to direct the downstream wafer fabrication process to that specific mask map. In another embodiment, providing the mask map to the downstream wafer fabrication process can include encoding a location of the mask map and allowing the downstream wafer fabrication process to decode the location. This encoding can include using a barcode, which could be located on the mask.
A method of optimizing a wafer fabrication process for a mask is also provided. The method comprises capturing an image of a mask and simulating a wafer image of the mask. A mask map of information can then be generated based on the simulation. This mask map can be provided to a downstream wafer fabrication process when such process involves the mask. In accordance with one aspect of the invention, at least one input parameter to the downstream wafer fabrication process can be changed based on the mask map.
The downstream wafer fabrication process can include a lithographic process, a resist process, and/or an etch process. If the downstream wafer fabrication process includes a lithographic process, then the parameter can include at least one of a type of illumination, a numerical aperture, a wavelength, a beam coherence, polarization mode, and an exposure dose. If the downstream wafer fabrication process includes a resist process, then the parameter can include at least one of a type of resist, a thickness of the resist, and a resist exposure. If the downstream wafer fabrication process includes an etch process, then the parameter can include at least one of a type of etching, a pressure, and an energy.
A system of providing information to downstream wafer fabrication processes is also provided. The system comprises means for capturing an image of a mask, means for simulating the image as it would appear on a wafer, means for generating a mask map of information based on the simulating, and means for providing the mask map to a downstream wafer fabrication process when such process involves the mask. The means for providing the mask map to the downstream wafer fabrication process can include means for indicating a location of each element in the mask map. In one embodiment, the means for providing the mask map to the downstream wafer fabrication process includes means for encoding a location of the mask map and means for allowing the downstream wafer fabrication process to decode the location. The means for generating the mask map can include means for determining a critical dimension variance on the mask and/or means for determining an edge error variance on the mask.
An input file to a wafer fabrication process is also provided. The input file includes simulation information regarding a mask used in the wafer fabrication process, wherein the simulation information customizes one or more input parameters to the wafer fabrication process. The simulation information can include at least one of a critical dimension variance and an edge error variance on the mask. In one embodiment, at least one of the critical dimension variance and the edge error variance can be represented as a histogram. In another embodiment, the simulation information can further include a simulated wafer image.
A computer program product can also be provided. This computer program product comprises a computer usable medium having a computer readable program code embodied therein for causing a computer to provide information to downstream wafer fabrication processes. The computer readable program code
Bever Hoffman & Harms LLP
Harms Jeanette S.
Niebling John F.
Numerical Technologies Inc.
Stevenson André C
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