Simulating topography of a conductive material in a...

Data processing: measuring – calibrating – or testing – Measurement system – Dimensional determination

Reexamination Certificate

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C438S780000

Reexamination Certificate

active

11267776

ABSTRACT:
A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.

REFERENCES:
patent: 2004/0058255 (2004-03-01), Jessen et al.
patent: 2005/0146714 (2005-07-01), Kitamura et al.
S. Wolf,Silicon Processing for VLSI Eta, vol. 4;Deep Submicron Process Technology, Lattice Press, Sunset Beach, CA, USA, Dec. 2002, (all pages1-204).
Z. Stavreva, D. Zeidler, M. Plotner, G. Grasshoff and K. Drescher, “Chemical-mechanical polishing of copper for interconnect formation,”Microelectronic Engineering, vol. 33, pp. 249-257, 1997, 9 Pages.
L. He, A. B. Kahng, K. Tam and J. Xiong, “Design of IC interconnects with accurate modeling of CMP,”International Society for Optical Engineering (SPIE) Symposium on Microlithograhpy, Mar. 2005, 11 pages.
V. Mehrotra, “Modeling the effects of systematic process variation on circuit performance,”Ph. D. Dissertation, Dept. of EECS, MIT, Cambridge, MA, USA, 2001, pp. 1-156.
T. H. Park, “Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits,”Ph.D. Dissertation, Dept. of EECS, MIT, Cambridge, MA, USA, 2002, ppl-204.
M. X. Yang, D. Mao, C. Yu, J. Dukovic and M. Xi, “Sub-100nm interconnects using multistep plating,”Solid State Technology, Oct. 2003, pp 4 total.
J. Reid, S. Mayer, E. Broadbent, E. Klawuhn and K. Ashtiani, “Factors influencing damascene feature fill using copper PVD and electroplating,”Solid State Technology, Jul. 2000, pp. 10 total.
T. P. Moffat, D. Wheeler, W. H. Huber and D. Josell, “Superconformal electrodeposition of copper,” Electrochemical and Solid-State Letters, vol. 4, pp. C26-C29, 2001.
D. Josell, D. Wheeler, W. H. Huber, J. E. Bonevich and T. P. Moffat, “A simple equation for predicting superconformal electrodeposition in submicrometer trenches,”Journal of the Electrochemical Society, vol. 148, pp. C767-C773, 2001, 7 pages.
Y. H. Im, M. O. Bloomfield, S. Sen and T. S. Cale, “Modeling pattern density dependent bump formation in copper electrochemical deposition,”Electrochemical and Solid State Letters, vol. 6, pp. C42-C46, 2003, 5 pages.
“Modeling of Pattern Dependencies in Multi-Step Copper Chemical Mechanical Polishing Processes”, Tamba Tugbawa et al., Published in Chemical-Mechanical Planarization for Multilevel Interconnect, Mar. 2001, All Pages, 4 pages, 1-4.
“Wafer-Scale CMP Modeling of With-in Wafer Non-Uniformity” Jianfeng Luo et al., Published in Laboratory for Manufacturing Automation, 2003, All Pages 1-24.
“Characterization and Modeling of Oxide Chemical-Mechanical Polishing Using Planarization Length and Pattern Density Concepts”, D. Okumu Ouma et al., Published in IEEE Transactions on Semiconductor Manufacturing, vol. 15, May 2, 2002, All Pages 1-13.
“Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Processes”, Tamba E. Gbondo-Tugbawa, Published in Massachusetts Institute of Technology, May 2002, All Pages.
“Review of Chemical-Mechanical Planarization Modeling for Integrated Circuit Fabrication: From Particle Scale to Die and Wafer Scales”, Jianfeng Luo, NSF and UC-SMART, believed to be published in 2003 or earlier, all pages 1-23.
“The Chemistry of additives in damascene copper plating” by P. M. Vereecken et al. Published in IBM J. Res & Dev. vol. 49, No. 1, Jan. 2005, All Pages 1-16.

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