Simulating circuit for magnetic tunnel junction device

Details Simulating circuit for magnetic tunnel junction device Simulating circuit for magnetic tunnel junction device

2006-01-05

2009-06-30

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S173000

Reexamination Certificate

active

07554838

ABSTRACT:
A simulating circuit for simulating the operation of a magnetic tunnel junction (MTJ) device having at least a free layer and a fixed layer is provided. The simulating circuit includes a closed switch loop for simulating the magnetization of the free layer and the fixed layer, thus for simulating the data recording, wherein the magnetization includes parallel state or anti-parallel state; a first write loop for simulating the first quadrant of the operation region of the MTJ device; a second write loop, a third write loop, and a fourth write loop for simulating the second quadrant, the third quadrant, and the fourth quadrant of the operation regions, respectively; a first resistor for simulating the wire resistance of the bit lines; a second resistor for simulating the wire resistance of the write word lines; and a third resistor for simulating the resistance of the magnetic MTJ device.

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Cho et al., A CMOS Macro-Madel for MTJ Resistor of MRAM Cell, 2004, phys. Stat. Sol. (a) 201, No. 8, pp. 1653-1657/DOI 10,1002/pssa.200304613.
Kim et al, Maro Model and Sense Amplifier for a MRAM, Dec. 2002, Journal of the Korean Physical Society, vol. 41, No. 6, pp. 896-901.

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