Simulated circuit layout for low voltage, low paper and high...

Details Simulated circuit layout for low voltage, low paper and high... Simulated circuit layout for low voltage, low paper and high...

2005-08-16

2005-08-16

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06931605

ABSTRACT:
The present invention relates to a current conveyor circuit capable of operating at very low voltages, said circuit comprising: three LVCM's and four MOSFETS, wherein LVCM1provides a constant bias current to flow through M3, if port X is kept open and the difference between the bias current and the injected current flows through M3if a current is injected into port X, which gets reflected at port Z due to the action of LVCM1, M3and M4, LVCM2maintains the drain currents of M1and M2constant, and LVCM3maintains a constant tail current in the circuit.

REFERENCES:
patent: 4329639 (1982-05-01), Davis
patent: 4897596 (1990-01-01), Hughes et al.
patent: 5512816 (1996-04-01), Lambert
patent: 6433528 (2002-08-01), Bonelli et al.
Wang et al., “The Design Methods of Current -Mode nth-Order Filter”, Jul. 2000, IEEE Proceedings of the 3rdWorld Congress o Intelligent Control and Automation, vol. 4, pp. 2570-2571.
Rajput et al., “Low Power, High PerformanceCurrent Mirror for Portable Analogue and Mixed Mode Applications”, Oct. 2001, IE Proceedings on Circuits, Devices and Systems, vol. 148, iss. 5, pp. 273-278.

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