Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-01-20
2001-04-10
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S714000, C438S720000
Reexamination Certificate
active
06214737
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to making sub-lithographic structures using sidewall patterning techniques. In particular, the present invention relates to sub 100 nm conductive structures using sidewall patterning techniques.
BACKGROUND ART
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This includes the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features. Since numerous interconnecting lines are typically present on a semiconductor wafer, the trend toward higher device densities is a notable concern.
The requirement of small features (and close spacing between adjacent features) requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photomask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photomask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. However, lithography is not without limitations. Patterning features having dimensions of about 0.25 &mgr;m or less with acceptable resolution is difficult at best, and impossible in some circumstances. Patterning conductive features including metal lines and silicon substances (such as amorphous silicon and polysilicon) with small dimensions is required in order to participate in the continuing trend toward higher device densities. Procedures that increase resolution, improve critical dimension control, and provide small conductive features are therefore desired.
SUMMARY OF THE INVENTION
The present invention provides methods of forming sub-lithographic features. The present invention also provides sub-lithographic conductive features that are particularly useful for forming metal lines, gate conductors and interconnects. As a result, the present invention effectively addresses the concerns raised by the trend towards the miniaturization of semiconductor devices.
In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a mask over a first portion of the conductive film wherein a second portion of the conductive film is exposed; partially etching the second portion of the conductive film to reduce the thickness of the second portion without completely removing the second portion thereby forming a sidewall in the conductive film; removing the mask; depositing a sidewall film over the conductive film, the sidewall film having a vertical portion adjacent the sidewall of the conductive film and a horizontal portion in areas not adjacent the sidewall of the conductive film; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; and etching the third portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
In another embodiment, the present invention relates to a method of forming a polysilicon structure, involving the steps of providing a substrate having a polysilicon film thereon; patterning a photoresist over a first portion of the polysilicon film exposing a second portion of the polysilicon film; partially etching the second portion of the polysilicon film to reduce the thickness of the second portion without completely removing the second portion thereby forming a sidewall in the polysilicon film; removing the photoresist; depositing uniformly a sidewall film over the polysilicon film, the sidewall film having a thickness from about 100 Å to about 2,000 Å and a vertical portion adjacent the sidewall of the polysilicon film; directionally etching the sidewall film exposing a third portion of the polysilicon film while substantially retaining the vertical portion of the sidewall film adjacent the sidewall; and etching the third portion of the polysilicon film thereby providing the polysilicon structure underlying the vertical portion of the sidewall film.
In yet another embodiment, the present invention relates to a method of forming a thin metal line, involving the steps of providing a substrate having a metal layer thereon; patterning a photoresist over a first portion of the metal layer exposing a second portion of the metal layer; partially etching the second portion of the metal layer to reduce the thickness of the second portion without completely removing the second portion thereby forming a sidewall in the metal layer; removing the photoresist; depositing uniformly a silicon containing film over the metal layer, the silicon containing film having a thickness from about 100 Å to about 2,000 Å and a vertical portion adjacent the sidewall of the metal layer; directionally etching the silicon containing film exposing a third portion of the metal layer while substantially retaining the vertical portion of the silicon containing film adjacent the sidewall; and etching the third portion of the metal layer thereby providing the thin metal line underlying the vertical portion of the silicon containing film.
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Early Kathleen R.
Lyons Christopher F.
Templeton Michael K.
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Utech Benjamin L.
Vinh Lan
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