Simplified low power flash write operation

Details Simplified low power flash write operation Simplified low power flash write operation

1991-06-12

1994-04-19

Zazworsky, John

Static information storage and retrieval

Read/write circuit

For complementary information

365218, 365900, G11C 700, G11C 800, G11C 1124

Patent

active

053052633

ABSTRACT:
In the preferred embodiment of the present invention flash write, a simultaneous and substantially identical write operation to a selected plurality of memory cells, is performed by splitting the pull up of the p sense amplifier transistors. The p sense amplifier transistor on digit is connected to V.sub.cc at its drain through a first pull up transistor and the p sense amplifier transistor on digit bar is connected to V.sub.cc at its drain through a second pull up transistor. A logic circuit generates control logic that actuates either both pull up transistors to initiate a typical read/write operation of a single memory cell or actuates one of the two pull up transistors to initiate a flash write to all of the memory cells on the selected wordline.

REFERENCES:
patent: 5140553 (1992-08-01), Choi et al.
patent: 5155705 (1992-10-01), Goto et al.

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