Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-06
1998-09-01
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711144, 711207, 711108, G06F 1208
Patent
active
058025685
ABSTRACT:
A simplified or pseudo least-recently-used (LRU) process and circuit in a cache memory or translation lookaside table (TLB) maintains status bits to identify which entries are valid and which entries have been recently used. If none of the entries are invalid, only entries not indicated as recently used are replaced (or overwritten). When all entries are indicated as valid and recently used, status bits other than the status bits for the entry last accessed are changed to indicate that the corresponding entries have not been recently used. Accordingly, those entries can be replaced, but the most recently used entry still cannot be replaced. This makes the pseudo LRU process closer to a full LRU process when compared to pseudo LRU processes which clear all status bits simultaneously. Complexity for the LRU process is not greatly increased because the address generated for the most recent access of an entry can be used to identify the bit which is not changed.
REFERENCES:
patent: 5329627 (1994-07-01), Nanda et al.
patent: 5353425 (1994-10-01), Malamy et al.
Bragdon Reginald G.
Chan Eddie P.
Millers David T.
Sun Microsystems Inc.
LandOfFree
Simplified least-recently-used entry replacement in associative does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simplified least-recently-used entry replacement in associative , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simplified least-recently-used entry replacement in associative will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-284541