Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-09-28
2001-01-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C250S559430, C250S559420, C250S559190, C250S559050, C250S559420, C356S241400, C356S237600, C356S243400, C700S110000, C700S121000
Reexamination Certificate
active
06177287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a methodology for the efficient review of defects detected during the manufacture of high performance semiconductor devices. Even more specifically, this invention relates to a methodology for the efficient review of defect images for selected defects detected and classified during the manufacture of high performance semiconductor devices.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects caused by the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect increases the cost of the remaining usable chips.
A single semiconductor wafer can require numerous process steps such as an oxidation step, an etch process, a metallization process, rapid thermal anneal (RTA) and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits. A major part of the analysis process is to determine if defects are caused by one of the process tools, and if so, which tool caused the defects.
As the wafer is placed into different tools during manufacture, each of the tools can produce different types of particles that drop onto the wafer and cause defects that have the potential to decrease the yield. In order to develop high yield semiconductor processes and to improve existing ones, it is important to identify the sources of the various particles that cause defects and then to prevent the tools from dropping these particles onto the wafer while the wafers are in the tools.
In order to be able to quickly resolve process or equipment issues in the manufacture of semiconductor products, a great deal of time, effort and money is being expended by semiconductor manufacturers to capture and classify silicon based defects. Once a defect is caught and properly described and classified, only then can work begin to resolve the cause of the defect and to eliminate the cause of the defect.
The methods of classifying a defect include making and storing an image of certain defects for evaluation. Because the evaluation of defects images is time intensive, it is necessary to store images for later evaluation. In addition, because storage of defect images is memory intensive, it is not practical to store image data for all defects. The defect image data is stored in an image storage system and classification data is stored in a defect management system. In order for a reviewer to review and evaluate defects, it is necessary for the reviewer to search both the defect management system and the defect image storage system to determine if there is image data corresponding to the classification data.
Therefore, what is needed is a method of storing image data and classification data in such a way that an evaluator can determine immediately if there is image data corresponding to the classification data for a particular defect.
SUMMARY OF THE INVENTION
The present invention overcomes the above problems of prior art defect evaluation methodologies through a method of storing classification data in defect management system and image data in a an image storage system. Identification data is sent to both the defect management system and the image storage system. The image storage system sends a cookie to the defect management system that allows the defect management system to identify those defects that have a captured image.
In accordance with an aspect of the invention, the identification data sent to the defect management system and the image storage system includes a production lot number, a wafer number, a layer number and a defect number.
In accordance with another aspect of the invention, an operator controlled review station can immediately display the defect classification data and image data for those defects that are identified a shaving corresponding image data.
The described method provides an improved method of evaluating defect data by allowing a reviewer to review and evaluate the classification data and image data for defects that are identified as having corresponding images. The classification data and image data is reviewed at an operator controlled review station that displays defect data and identifies those defects that have corresponding images thus allowing the reviewer to select those defects that have corresponding images.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5129009 (1992-07-01), Lebeau
patent: 5479252 (1995-12-01), Worster et al.
patent: 5801965 (1998-09-01), Takagi et al.
patent: 5862055 (1999-01-01), Chen et al.
patent: 5917588 (1999-06-01), Addiego
patent: 5943437 (1999-08-01), Sumie et al.
patent: 5966459 (1999-10-01), Chen et al.
patent: 5999003 (1999-12-01), Steffan et al.
patent: 6011619 (2000-01-01), Steffan et al.
patent: 6035244 (2000-03-01), Chen et al.
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Hach Jonathan
Nelson H. Donald
Niebling John F.
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