Simplified dual damascene process

Details Simplified dual damascene process Simplified dual damascene process

2006-03-21

2006-03-21

Smith, Bradley K. (Department: 2891)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S618000, C438S623000, C438S734000, C438S735000, C438S737000

Reexamination Certificate

active

07015149

ABSTRACT:
A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).

REFERENCES:
patent: 6066569 (2000-05-01), Tobben
patent: 6174596 (2001-01-01), Lee
patent: 6514860 (2003-02-01), Okada et al.
patent: 6812131 (2004-11-01), Kennedy et al.

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